Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2011, Pages 227-236

  Luu, Jason ^a   Anderson, Jason Helge ^a   Rose, Jonathan Scott ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE DESCRIPTION; CAD FLOW; COMPLEX LOGIC BLOCKS; DESCRIPTION LANGUAGES; FPGA FABRIC; HARD BLOCKS; KEY PARTS; LOGIC BLOCKS; LOWER BOUNDS; MODES OF OPERATION; NUMBER OF BLOCKS; SOFT LOGIC; VERILOG;

ARCHITECTURE; LOGIC GATES; MEMORY ARCHITECTURE;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 79952957517     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1950413.1950457     Document Type: Conference Paper

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