A junctionless nanowire transistor with a dual-material gate

IEEE Transactions on Electron Devices

Volumn 59, Issue 7, 2012, Pages 1829-1836

  Lou, Haijun ^a   Zhang, Lining ^a   Zhu, Yunxi ^a   Lin, Xinnan ^a   Yang, Shengqi ^b   He, Jin ^a   Chan, Mansun ^c  

^a PEKING UNIVERSITY   (China)

^b SHANGHAI UNIVERSITY   (China)

^c HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

Dual material gate (DMG); junctionless; nanowire; numerical simulation; single material gate (SMG)

Indexed keywords

3-D NUMERICAL SIMULATION; CONTROL GATES; DRAIN-INDUCED BARRIER LOWERING; DUAL-MATERIAL GATE (DMG); JUNCTIONLESS; MAXIMUM OSCILLATION FREQUENCY; NANOWIRE TRANSISTORS; ON/OFF CURRENT RATIO; SINGLE-MATERIAL GATE (SMG); UNITY-GAIN FREQUENCIES; WORK-FUNCTION DIFFERENCE;

COMPUTER SIMULATION; DRAIN CURRENT; NANOWIRES;

MATERIALS;

EID: 84862677604     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2012.2192499     Document Type: Article

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