High-performance ultra-low power junctionless nanowire FET on SOI substrate in subthreshold logic application

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2010, Pages

  Chen, Chun Yu ^a   Lin, Jyi Tsong ^a   Chiang, Meng Hsueh ^b   Kim, Keunwoo ^c  

^a NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

^b NATIONAL ILAN UNIVERSITY   (Taiwan)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DRIVE CURRENTS; NANOWIRE FET; NUMERICAL SIMULATION; SOI SUBSTRATES; SUBTHRESHOLD LOGIC; ULTRA-LOW POWER; WIRE DIAMETER;

COMPUTER SIMULATION; FIELD EFFECT TRANSISTORS; NANOWIRES;

MESFET DEVICES;

EID: 78650554250     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOI.2010.5641061     Document Type: Conference Paper

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