A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gate

IEEE Electron Device Letters

Volumn 25, Issue 8, 2004, Pages 580-582

  Ren, C ^a   Yu, H Y ^a   Kang, J F ^b   Wang, X P ^a   Ma, H H H ^a   Yeo, Yee Chia ^a   Chan, Daniel S H ^a   Li, M F ^a,c   Kwong, D L ^d  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b PEKING UNIVERSITY   (China)

^c INSTITUTE OF MICROELECTRONICS   (Singapore)

^d The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; ELECTRIC BREAKDOWN; ELECTRODES; ETCHING; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; HIGH TEMPERATURE APPLICATIONS; LEAKAGE CURRENTS; METALLORGANIC CHEMICAL VAPOR DEPOSITION; SEMICONDUCTOR JUNCTIONS; THERMODYNAMIC STABILITY;

EQUIVALENT OXIDE THICKNESS; GATE DIELECTRICS; GATE LEAKAGE; METAL GATE ELECTRODES; TIME DEPENDENT DIELECTRIC BREAKDOWN CHARACTERISTICS;

MOSFET DEVICES;

EID: 3943106164     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.832535     Document Type: Article

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