Numerical investigation on the junctionless nanowire FET

2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011

Volumn , Issue , 2011, Pages 7-10

  Gnani, E ^a   Gnudi, A ^a   Reggiani, S ^a   Baccarani, G ^a   Shen, N ^b   Singh, N ^b   Lo, G Q ^b   Kwong, D L ^b  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CYLINDRICAL GEOMETRY; ELECTRICAL PROPERTY; ELECTROSTATIC POTENTIALS; FUTURE TECHNOLOGIES; I-V AND C-V CHARACTERISTICS; NANOWIRE FET; NUMERICAL INVESTIGATIONS; NUMERICAL MODELS; NUMERICAL RESULTS; NUMERICAL SIMULATION; TURN-ON CHARACTERISTICS;

CARRIER CONCENTRATION; COMPUTER SIMULATION; CYLINDERS (SHAPES); ELECTRIC PROPERTIES; MESFET DEVICES; NANOWIRES;

ELECTRIC WIRE;

EID: 79958015315     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ULIS.2011.5757981     Document Type: Conference Paper

References (5)

1. C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J. P. Colinge, "Junctionless multigate field-effect transistor," Applied Physics Letters, vol. 94, p. 053511, 2009.
2. J. P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy, and R. Murphy, "Nanowire transistors without junctions," Nature Nanotechnology, vol. 5, 2010.
3. C.-W. Lee, A. Borne, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, and J. P. Colinge, "High Temperature Performance of Silicon Junctionless MOSFETs," IEEE Trans. on Electron Devices, vol. 53, no. 3, pp. 620-625, 2010.
4. B. Yang, K. D. Buddharaju, S. H. G. Teo, N. Singh, G. Q. Lo, and D. L. Kwong, "Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET," IEEE Electron Device Letters, vol. 29, no. 7, pp. 791-794, 2008.
5. S. Inc., Sentaurus Device Users' Manual, Release Version C-2009.06, 2009.