-
1
-
-
84886447996
-
"Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel"
-
H.-S. Wong, K. K. Chan, and Y. Taur, "Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel," in IEDM Tech. Dig., 1997, pp. 427-430.
-
(1997)
IEDM Tech. Dig.
, pp. 427-430
-
-
Wong, H.-S.1
Chan, K.K.2
Taur, Y.3
-
2
-
-
10844274151
-
"High performance double-gate device technology challenges and oppurtunities"
-
Mar.18-21
-
M. Ieong, H.-S. P. Wong, E. Nowak, J. Kedzierski, and E. C. Jones, "High performance double-gate device technology challenges and oppurtunities" in Proc. ISQED, Mar.18-21, 2002, pp.492-95.
-
(2002)
Proc. ISQED
, pp. 492-495
-
-
Ieong, M.1
Wong, H.-S.P.2
Nowak, E.3
Kedzierski, J.4
Jones, E.C.5
-
3
-
-
0033329310
-
"Sub-50-nm FinFET: PMOS"
-
X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Sub-50-nm FinFET: PMOS," in IEDM Tech. Dig. 1999, pp. 67-70.
-
(1999)
IEDM Tech. Dig.
, pp. 67-70
-
-
Huang, X.1
Lee, W.-C.2
Kuo, C.3
Hisamoto, D.4
Chang, L.5
Kedzierski, J.6
Anderson, E.7
Takeuchi, H.8
Choi, Y.-K.9
Asano, K.10
Subramanian, V.11
King, T.-J.12
Bokor, J.13
Hu, C.14
-
4
-
-
0035716615
-
"3D analytical subthreshold and quantum mechanical analyzes of double-gate MOSFET"
-
G. Pei, V. Narayanan, Z. Liu, and E. C. Kan, "3D analytical subthreshold and quantum mechanical analyzes of double-gate MOSFET " in IEDM Tech. Dig., 2001, pp. 103-106.
-
(2001)
IEDM Tech. Dig.
, pp. 103-106
-
-
Pei, G.1
Narayanan, V.2
Liu, Z.3
Kan, E.C.4
-
5
-
-
0036494144
-
"A spacer patterning technology for nanoscale CMOS"
-
Mar
-
Y.-K. Choi, T.-J. King, and C. Hu, "A spacer patterning technology for nanoscale CMOS," IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 436---441, Mar. 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, Issue.3
, pp. 436-441
-
-
Choi, Y.-K.1
King, T.-J.2
Hu, C.3
-
6
-
-
0035714369
-
"High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices"
-
J. Kedzierski, D. M. Fried, E. J. Nowak, T. Kanarsky, J. H. Rankin, H. Hanafi, W. Natzle, D. Boyd, Y. Zhang, R. A. Roy, J. Newbury, C. Yu, Q. Yang, P. Saunders, C. P. Willets, A. Johnson, S. P. Cole, H. E. Young, N. Carpenter, D. Rakowski, B. A. Rainey, P. E. Cottrell, M. Ieong, and H.-S. P. Wong, "High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices," in IEDM Tech. Dig., 2001, pp. 437-440.
-
(2001)
IEDM Tech. Dig.
, pp. 437-440
-
-
Kdzierski, J.1
Fried, D.M.2
Nowak, E.J.3
Kanarsky, T.4
Rankin, J.H.5
Hanafi, H.6
Natzle, W.7
Boyd, D.8
Zhang, Y.9
Roy, R.A.10
Newbury, J.11
Yu, C.12
Yang, Q.13
Saunders, P.14
Willets, C.P.15
Johnson, A.16
Cole, S.P.17
Young, H.E.18
Carpenter, N.19
Rakowski, D.20
Rainey, B.A.21
Cottrell, P.E.22
Ieong, M.23
Wong, H.-S.P.24
more..
-
7
-
-
29044440093
-
"FinFET--A self-aligned double-gate MOSFET scalable to 20 nm"
-
Dec
-
D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, "FinFET--A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, Dec. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, Issue.12
, pp. 2320-2325
-
-
Hisamoto, D.1
Lee, W.-C.2
Kedzierski, J.3
Takeuchi, H.4
Asano, K.5
Kuo, C.6
Anderson, E.7
King, T.-J.8
Bokor, J.9
Hu, C.10
-
8
-
-
0041886632
-
"Ideal 0rectangular cross section Si-Fin channel double-gate MOSFETs fabricated using orientation-dependent wet etching"
-
May
-
Y. Liu, K. Ishii, T. Tsutsumi, M. Masahara, and E. Suzuki, "Ideal rectangular cross section Si-Fin channel double-gate MOSFETs fabricated using orientation-dependent wet etching," IEEE Electron Device Lett., vol. 24, no. 5, pp. 484-486, May 2003.
-
(2003)
IEEE Electron Device Lett.
, vol.24
, Issue.5
, pp. 484-486
-
-
Liu, Y.1
Ishii, K.2
Tsutsumi, T.3
Masahara, M.4
Suzuki, E.5
-
9
-
-
84964685852
-
"Mechanical cell lysis result of a sample preparation module for functional genomics"
-
May 2-4
-
D. D. Carlo and L. P. Lee, "Mechanical cell lysis result of a sample preparation module for functional genomics," in Proc. IEEE Microtechnologies in Medicine Biology Conf., May 2-4, 2002, pp. 527-30.
-
(2002)
Proc. IEEE Microtechnologies in Medicine Biology Conf.
, pp. 527-530
-
-
Carlo, D.D.1
Lee, L.P.2
-
10
-
-
0035475617
-
"Sub-60-nm quasiplanar FinFETs fabricated using a simplified process"
-
May
-
N. Lindert, L. Chang, Y.-K. Choi, E. H. Anderson, W.-C. Lee, T.-J. King, J. Bokor, and C. Hu, "Sub-60-nm quasiplanar FinFETs fabricated using a simplified process," IEEE Electron Device Lett., vol. 22, no. 5, pp. 487-489, May 2001.
-
(2001)
IEEE Electron Device Lett.
, vol.22
, Issue.5
, pp. 487-489
-
-
Lindert, N.1
Chang, L.2
Choi, Y.-K.3
Anderson, E.H.4
Lee, W.-C.5
King, T.-J.6
Bokor, J.7
Hu, C.8
-
11
-
-
0036923594
-
"Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation"
-
J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K.-L. Lee, B. A. Rainey, D. Fried, P. Cottrell, H.-S. P. Wong, M. Ieong, and W. Haensch, "Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation," in IEDM Tech. Dig., 2002, pp. 247-250.
-
(2002)
IEDM Tech. Dig.
, pp. 247-250
-
-
Kedzierski, J.1
Nowak, E.2
Kanarsky, T.3
Zhang, Y.4
Boyd, D.5
Carruthers, R.6
Cabral, C.7
Amos, R.8
Lavoie, C.9
Roy, R.10
Newbury, J.11
Sullivan, E.12
Benedict, J.13
Saunders, P.14
Wong, K.15
Canaperi, D.16
Krishnan, M.17
Lee, K.-L.18
Rainey, B.A.19
Fried, D.20
Cottrell, P.21
Wong, H.-S.P.22
Ieong, M.23
Haensch, W.24
more..
-
12
-
-
0036923438
-
"FinFET scaling to 10 nm gate length"
-
B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M. Lin, and D. Kyser, "FinFET scaling to 10 nm gate length," in IEDM Tech. Dig., 2002, pp. 251-254.
-
(2002)
IEDM Tech. Dig.
, pp. 251-254
-
-
Yu, B.1
Chang, L.2
Ahmed, S.3
Wang, H.4
Bell, S.5
Yang, C.6
Tabery, C.7
Ho, C.8
Xiang, Q.9
King, T.-J.10
Bokor, J.11
Hu, C.12
Lin, M.13
Kyser, D.14
-
13
-
-
0036478129
-
"Modeling of photoresist erosion in plasma etching processes"
-
Feb
-
D. Zhang, S. Rauf, and T. Sparks, "Modeling of photoresist erosion in plasma etching processes," IEEE Trans. Plasma Sci., vol. 30, no. 1, pp. 114-115, Feb. 2002.
-
(2002)
IEEE Trans. Plasma Sci.
, vol.30
, Issue.1
, pp. 114-115
-
-
Zhang, D.1
Rauf, S.2
Sparks, T.3
-
14
-
-
0141761522
-
"Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers"
-
Jun. 10-12
-
T. Park, S. Choi, D. H. Lee, J. R. Yoo, B. C. Lee, J. Y. Kim, C. G. Lee, K. K. Choi, S. J. Hyun, Y. G. Shin, J. N. Han, I. S. Park, U. I. Chung, J. T. Moon, E. Yoon, and J. H. Lee, "Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers," in VSLI Symp. Tech. Dig., Jun. 10-12, 2003, pp. 135-136.
-
(2003)
VSLI Symp. Tech. Dig.
, pp. 135-136
-
-
Park, T.1
Choi, S.2
Lee, D.H.3
Yoo, J.R.4
Lee, B.C.5
Kim, J.Y.6
Lee, C.G.7
Choi, K.K.8
Hyun, S.J.9
Shin, Y.G.10
Han, J.N.11
Park, I.S.12
Chung, U.I.13
Moon, J.T.14
Yoon, E.15
Lee, J.H.16
-
15
-
-
0034860289
-
"A sub-40 nm body thickness N-type FinFET"
-
Jun
-
D.M. Fried, A. P. Johnson, E. J. Nowak, J. H. Rankin, and C. R. Willets, "A sub-40 nm body thickness N-type FinFET," in Device Research Conf., Jun. 2001, pp. 24-25.
-
(2001)
Device Research Conf.
, pp. 24-25
-
-
Fried, D.M.1
Johnson, A.P.2
Nowak, E.J.3
Rankin, J.H.4
Willets, C.R.5
-
16
-
-
0036611198
-
"A comprehansive analytical subthreshold swing (S) model for double-gate MOSFETs"
-
Aug
-
Q. Chen, B. Agrawal, and J. D. Meindl, "A comprehansive analytical subthreshold swing (S) model for double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 49, no. 8, pp. 1086-90, Aug. 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, Issue.8
, pp. 1086-1090
-
-
Chen, Q.1
Agrawal, B.2
Meindl, J.D.3
-
18
-
-
0004245602
-
International Technology Roadmap for Semiconductors
-
San Jose, CA
-
International Technology Roadmap for Semiconductors, San Jose, CA. Online. Available: http://www.itrs.org
-
-
-
|