Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET

IEEE Transactions on Electron Devices

Volumn 51, Issue 9, 2004, Pages 1463-1467

  Chaudhry, Anurag ^a   Kumar, M Jagadesh ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

[No Author keywords available]

Indexed keywords

CARRIER TRANSPORT EFFICIENCY; FULLY DEPLETED DUAL MATERIAL GATE; GATE MATERIAL ENGINEERING; SHORT CHANNEL EFFECTS; TRANSCONDUCTANCE ENHANCEMENT; TRANSCONDUCTANCE SUPPRESSION;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRON TRANSPORT PROPERTIES; GATES (TRANSISTOR); SEMICONDUCTOR DEVICE STRUCTURES; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

MOSFET DEVICES;

EID: 4444274252     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.833961     Document Type: Article

References (14)

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