메뉴 건너뛰기




Volumn 58, Issue 5, 2011, Pages 1388-1396

RF performance and small-signal parameter extraction of junctionless silicon nanowire MOSFETs

Author keywords

Device simulation; junctionless (JL); metaloxidesemiconductor field effect transistor (MOSFET); modeling; non quasi static (NQS); parameter extraction; radio frequency (RF); silicon nanowire (SNW)

Indexed keywords

DEVICE SIMULATIONS; JUNCTIONLESS (JL); METALOXIDESEMICONDUCTOR FIELD-EFFECT TRANSISTOR (MOSFET); MODELING; NON QUASI STATIC; RADIO FREQUENCY (RF); SILICON NANOWIRE (SNW);

EID: 79955543452     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2109724     Document Type: Article
Times cited : (193)

References (36)
  • 1
    • 58149218289 scopus 로고    scopus 로고
    • Spice modeling of silicon nanowire field-effect transistors for high-speed analog integrated circuits
    • Nov
    • S. Hamedi-Hagh and A. Bindal, "Spice modeling of silicon nanowire field-effect transistors for high-speed analog integrated circuits," IEEE Trans. Nanotechnol., vol. 7, no. 6, pp. 766-775, Nov. 2008.
    • (2008) IEEE Trans. Nanotechnol. , vol.7 , Issue.6 , pp. 766-775
    • Hamedi-Hagh, S.1    Bindal, A.2
  • 2
    • 77956894726 scopus 로고    scopus 로고
    • NANOCAD framework for simulation of quantum effects in nanoscale MOSFET de-vices
    • Mar
    • S. Jin, C H. Park, I.-Y. Chung, Y. J. Park, and H. S. Min, "NANOCAD framework for simulation of quantum effects in nanoscale MOSFET de-vices," J. Semicond. Technol. Sci., vol. 6, no. 1, pp. 1-9, Mar. 2006.
    • (2006) J. Semicond. Technol. Sci. , vol.6 , Issue.1 , pp. 1-9
    • Jin, S.1    Park, C.H.2    Chung, I.-Y.3    Park, Y.J.4    Min, H.S.5
  • 4
    • 33847367048 scopus 로고    scopus 로고
    • Source/drain extension region engineering in FinFETs for low-voltage analog applications
    • DOI 10.1109/LED.2006.889239
    • A. Kranti and G. A. Armstrong, "Source/drain extension region engi-neering in FinFETs for low-voltage analog applications," IEEE Electron Device Lett., vol. 28, no. 2, pp. 139-141, Feb. 2007. (Pubitemid 46336445)
    • (2007) IEEE Electron Device Letters , vol.28 , Issue.2 , pp. 139-141
    • Kranti, A.1    Armstrong, G.A.2
  • 6
    • 0036867952 scopus 로고    scopus 로고
    • A computational study of thin-body, double-gate, Schottky barrier MOSFETs
    • Nov
    • J. Guo and M. S. Lundstrom, "A computational study of thin-body, double-gate, Schottky barrier MOSFETs," IEEE Trans. Electron Devices, vol. 49, no. 11, pp. 1897-1902, Nov. 2002.
    • (2002) IEEE Trans. Electron Devices , vol.49 , Issue.11 , pp. 1897-1902
    • Guo, J.1    Lundstrom, M.S.2
  • 7
    • 23344435702 scopus 로고    scopus 로고
    • A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain
    • DOI 10.1109/TED.2005.852893
    • S. Xiong, T.-J. King, and J. Bokor, "A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain," IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1859-1867, Aug. 2005. (Pubitemid 41100651)
    • (2005) IEEE Transactions on Electron Devices , vol.52 , Issue.8 , pp. 1859-1867
    • Xiong, S.1    King, T.-J.2    Bokor, J.3
  • 8
    • 0023421993 scopus 로고
    • Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
    • F Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, "Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance," IEEE Electron Device Lett., vol. EDL-8, no. 9, pp. 410-412, Sep. 1987. (Pubitemid 17650855)
    • (1987) Electron device letters , vol.EDL-8 , Issue.9 , pp. 410-412
    • Balestra Francis1    Cristoloveanu Sorin2    Benachir Mohcine3    Brini Jean4    Elewa Tarek5
  • 10
    • 0036498428 scopus 로고    scopus 로고
    • Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: Optimization of the device architecture
    • DOI 10.1016/S0038-1101(01)00111-3, PII S0038110101001113
    • T. Ernst, C Tinella, and S. Cristoloveanu, "Fringing fields in sub-0.1 μ m fully depleted SOI MOSFETs: Optimization of the device architecture," SolidState Electron., vol. 46, no. 3, pp. 373-378, Mar. 2002. (Pubitemid 34141225)
    • (2002) Solid-State Electronics , vol.46 , Issue.3 , pp. 373-378
    • Ernst, T.1    Tinella, C.2    Raynaud, C.3    Cristoloveanu, S.4
  • 11
    • 70349333942 scopus 로고    scopus 로고
    • A SPICE-compatible new silicon nanowire field-effect transistors (SNWFETs) model
    • Sep
    • S. H. Lee, Y S. Yu, S. W. Hwang, and D. Ahn, "A SPICE-compatible new silicon nanowire field-effect transistors (SNWFETs) model," IEEE Trans. Nanotechnol., vol. 8, no. 5, pp. 643-649, Sep. 2009.
    • (2009) IEEE Trans. Nanotechnol. , vol.8 , Issue.5 , pp. 643-649
    • Lee, S.H.1    Yu, Y.S.2    Hwang, S.W.3    Ahn, D.4
  • 13
    • 27644508759 scopus 로고    scopus 로고
    • Synthesis and postgrowthdopingof siliconnanowires
    • Fischer, and A. T. Johnson Nov
    • K. Byon, D. Tham, J. E. Fischer, and A. T. Johnson, "Synthesis and postgrowthdopingof siliconnanowires,"Appl. Phys.Lett., vol. 87, no. 19, pp. 193 104-1-193 104-3, Nov. 2005.
    • (2005) Appl. Phys.Lett. , vol.87 , Issue.19 , pp. 1931041-1931043
    • Byon, K.1    Tham, J.E.D.2
  • 14
    • 33751294582 scopus 로고    scopus 로고
    • Semiconductor nanowires
    • DOI 10.1088/0022-3727/39/21/R01, PII S0022372706105525, R01
    • W. Lu and C M. Lieber, "Semiconductor nanowires," J. Phys. D, Appl. Phys., vol. 39, no. 21, pp. R387-R406, Nov. 2006. (Pubitemid 44794183)
    • (2006) Journal of Physics D: Applied Physics , vol.39 , Issue.21
    • Lu, W.1    Lieber, C.M.2
  • 15
    • 32944456750 scopus 로고    scopus 로고
    • Current-voltage characteristics and parameter retrieval of semiconduct-ing nanowires
    • Feb
    • Z. Y Zhang, C H. Jin, X. L. Liang, Q. Chen, and L.-M. Peng, "Current-voltage characteristics and parameter retrieval of semiconduct-ing nanowires," Appl. Phys. Lett., vol. 88, no. 7, pp. 073 102-1-073 102-3, Feb. 2006.
    • (2006) Appl. Phys. Lett. , vol.88 , Issue.7 , pp. 0731021-0731023
    • Zhang, Z.Y.1    Jin, C.H.2    Liang, X.L.3    Chen, Q.4    Peng, L.-M.5
  • 16
    • 0038161696 scopus 로고    scopus 로고
    • High performance silicon nanowire field effect transistors
    • DOI 10.1021/nl025875l
    • Y Cui, Z. Zhong, D. Wang, W. Wang, and C M. Lieber, "High perfor-mance silicon nanowire field effect transistors," Nano Lett., vol. 3, no. 2, pp. 149-152, Feb. 2003. (Pubitemid 37130527)
    • (2003) Nano Letters , vol.3 , Issue.2 , pp. 149-152
    • Cui, Y.1    Zhong, Z.2    Wang, D.3    Wang, W.U.4    Lieber, C.M.5
  • 18
    • 56649095943 scopus 로고    scopus 로고
    • A com-pact model of silicon-based nanowire MOSFETs for circuit simulation and design
    • Nov
    • J. Yang, J. He, F Liu, L. Zhang, F Liu, X. Zhang, and M. Chan, "A com-pact model of silicon-based nanowire MOSFETs for circuit simulation and design," IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 2898-2906, Nov. 2008.
    • (2008) IEEE Trans. Electron Devices , vol.55 , Issue.11 , pp. 2898-2906
    • Yang, J.1    He, J.2    Liu, F.3    Zhang, L.4    Liu, F.5    Zhang, X.6    Chan, M.7
  • 20
    • 49249139665 scopus 로고    scopus 로고
    • Investigation of parasitic effects and design optimization in silicon nanowire MOS-FETs for RF applications
    • Aug
    • J. Zhunge, R. Wang, R. Huang, X. Zhang, and Y Wang, "Investigation of parasitic effects and design optimization in silicon nanowire MOS-FETs for RF applications," IEEE Trans. Electron Devices, vol. 55, no. 8, pp. 2142-2147, Aug. 2008.
    • (2008) IEEE Trans. Electron Devices , vol.55 , Issue.8 , pp. 2142-2147
    • Zhunge, J.1    Wang, R.2    Huang, R.3    Zhang, X.4    Wang, Y.5
  • 21
    • 69449084442 scopus 로고    scopus 로고
    • A review on compact modeling of multiple-gate MOSFETs
    • Aug
    • J. Song, B. Yu, Y Yuan, and Y Taur, "A review on compact modeling of multiple-gate MOSFETs," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 8, pp. 1858-1869, Aug. 2009.
    • (2009) IEEE Trans. Circuits Syst. I, Reg. Papers , vol.56 , Issue.8 , pp. 1858-1869
    • Song, J.1    Yu, B.2    Yuan, Y.3    Taur, Y.4
  • 27
    • 77950125219 scopus 로고    scopus 로고
    • A new robust non-local algorithm for band-to-band tunnel-ing simulation and its application to Tunnel-FET
    • Apr
    • C Shen, L. T. Yang, E.-H. Toh, C.-H. Heng, G. S. Samudra, and Y.-C. Yeo, "A new robust non-local algorithm for band-to-band tunnel-ing simulation and its application to Tunnel-FET," in Proc VLSI-TSA, Apr. 2009, pp. 113-114.
    • (2009) Proc VLSI-TSA , pp. 113-114
    • Shen, C.1    Yang, L.T.2    Toh, E.-H.3    Heng, C.-H.4    Samudra, G.S.5    Yeo, Y.-C.6
  • 28
    • 84943244173 scopus 로고    scopus 로고
    • Accurate four-terminal RF MOSFET model accounting for the short-channel effect in the source-to-drain capaci-tance
    • Sep
    • M. Je and H. Shin, "Accurate four-terminal RF MOSFET model accounting for the short-channel effect in the source-to-drain capaci-tance," in Proc Int. Conf. Simul. Semicond. Process. Devices, Sep. 2003, pp. 247-250.
    • (2003) Proc Int. Conf. Simul. Semicond. Process. Devices , pp. 247-250
    • Je, M.1    Shin, H.2
  • 29
    • 0025404175 scopus 로고
    • Conduction mechanisms in thin-film accumulation-mode SOI p-channel MOSFETs
    • Mar
    • J.-P. Colinge, "Conduction mechanisms in thin-film accumulation-mode SOI p-channel MOSFETs," IEEE Trans. Electron Devices, vol. 37, no. 3, pp. 718-723, Mar. 1990.
    • (1990) IEEE Trans. Electron Devices , vol.37 , Issue.3 , pp. 718-723
    • Colinge, J.-P.1
  • 31
    • 68849123869 scopus 로고    scopus 로고
    • DC baseband and high-frequency characteris-tics of a silicon nanowire field effect transistor circuit
    • Apr
    • Y Li and C.-H. Hwang, "DC baseband and high-frequency characteris-tics of a silicon nanowire field effect transistor circuit," Semicond. Sci. Technol., vol. 24, no. 4, pp. 045 004-1-045 004-8, Apr. 2009.
    • (2009) Semicond. Sci. Technol. , vol.24 , Issue.4 , pp. 0450041-0450048
    • Li, Y.1    Hwang, C.-H.2
  • 32
    • 77951572351 scopus 로고    scopus 로고
    • The effect of the geometry aspect ratio on the silicon ellipse-shaped surrounding-gate field-effect transistor and circuit
    • Sep
    • Y Li and C.-H. Hwang, "The effect of the geometry aspect ratio on the silicon ellipse-shaped surrounding-gate field-effect transistor and circuit," Semicond. Sci. Technol., vol. 24, no. 9, pp. 095 018-1-095 018-8, Sep. 2009.
    • (2009) Semicond. Sci. Technol. , vol.24 , Issue.9 , pp. 0950181-0950188
    • Li, Y.1    Hwang, C.-H.2
  • 34
    • 77957884874 scopus 로고    scopus 로고
    • Fabrication of highly scaled silicon nanowire gate-all-around metal-oxide-semiconductor field effect transistors by using self-aligned local-channel V-gate by optical lithography process
    • Aug
    • J. H. Park, J. Y Song, J. P. Kim, S. W. Kim, J.-G. Yun, and B.-G. Park, "Fabrication of highly scaled silicon nanowire gate-all-around metal-oxide-semiconductor field effect transistors by using self-aligned local-channel V-gate by optical lithography process," Jpn. J. Appl. Phys., Part 1, vol. 49, no. 8, pp. 84 203-1-84 203-5, Aug. 2010.
    • (2010) Jpn. J. Appl. Phys., Part 1 , vol.49 , Issue.8 , pp. 842031-842035
    • Park, J.H.1    Song, J.Y.2    Kim, J.P.3    Kim, S.W.4    Yun, J.-G.5    Park, B.-G.6
  • 35
    • 67649951491 scopus 로고    scopus 로고
    • Formation of Ge nanocrystal in a silicon dioxide layer using pulsed plasma-immersion ion implantation
    • Oct
    • Y M. Kim, M.-K. Jeong, K.-H. Park, S.-G. Jung, S.-H. Bae, and J.-H. Lee, "Formation of Ge nanocrystal in a silicon dioxide layer using pulsed plasma-immersion ion implantation," Microelectron. Eng., vol. 86, no. 10, pp. 2045-2048, Oct. 2009.
    • (2009) Microelectron. Eng. , vol.86 , Issue.10 , pp. 2045-2048
    • Kim, Y.M.1    Jeong, M.-K.2    Park, K.-H.3    Jung, S.-G.4    Bae, S.-H.5    Lee, J.-H.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.