Novel nanoscale device architecture to reduce leakage currents in logic circuits: A quantum-mechanical study

Semiconductor Science and Technology

Volumn 21, Issue 4, 2006, Pages 397-408

  Datta, Deepanjan ^a   Ganguly, Samiran ^a   Dasgupta, S ^b   Prasad Sarab, A Annada ^a  

^a INDIAN SCHOOL OF MINES   (India)

^b INDIAN INSTITUTE OF TECHNOLOGY ROORKEE   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL DESIGN; LEAKAGE CURRENTS; MOSFET DEVICES; NANOSTRUCTURED MATERIALS; NUMERICAL ANALYSIS; QUANTUM THEORY;

NANO-SCALE DOUBLE-GATE (DG) MOSFET ARCHITECTURE; NOVEL NANOSCALE DEVICES; PARALLEL CONNECTED HETERO-MATERIAL DOUBLE-GATE (PCHEM-DG) MOSFET; QUANTUM-MECHANICAL STUDY;

LOGIC CIRCUITS;

EID: 33644969674     PISSN: 02681242     EISSN: 13616641     Source Type: Journal    
DOI: 10.1088/0268-1242/21/4/001     Document Type: Article

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