Comparison of junctionless and conventional trigate transistors with L g down to 26 nm

IEEE Electron Device Letters

Volumn 32, Issue 9, 2011, Pages 1170-1172

  Rios, R ^a   Cappellani, A ^a   Armstrong, M ^a   Budrevich, A ^a   Gomez, H ^a   Pai, R ^a   Rahhal Orabi, N ^a   Kuhn, K ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Accumulation mode; inversion mode (IM); trigate

Indexed keywords

ACCUMULATION MODES; ANALYTIC MODELS; CHANNEL CHARGE; CHANNEL LENGTH; CHANNEL MOBILITY; DEGRADED BEHAVIOR; DEVICE SIMULATIONS; EXPERIMENTAL COMPARISON; GATE CAPACITANCE; GATE CONTROL; INVERSION MODES; OFF-STATE LEAKAGE; TRI-GATE TRANSISTORS; TRIGATE;

COMPUTER SIMULATION;

EQUIPMENT;

EID: 80052031065     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2011.2158978     Document Type: Article

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