Design considerations for novel device architecture: Hetero-material double-gate (HEM-DG) MOSFET with sub-100 nm gate length

Solid-State Electronics

Volumn 48, Issue 7, 2004, Pages 1169-1174

  Saxena, Manoj ^a   Haldar, Subhasis ^b   Gupta, Mridula ^c   Gupta, R S ^c  

^a UNIVERSITY OF DELHI   (India)

^b UNIVERSITY OF DELHI   (India)

^c UNIVERSITY OF DELHI   (India)

Author keywords

Characterization; DG MOSFET; DIBL; Hetero material gate

Indexed keywords

APPROXIMATION THEORY; COMPUTER SIMULATION; DIELECTRIC DEVICES; DIFFERENTIAL EQUATIONS; ELECTRIC FIELDS; GATES (TRANSISTOR); MATHEMATICAL MODELS; OPTIMIZATION; PERTURBATION TECHNIQUES; POISSON EQUATION; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS; THRESHOLD VOLTAGE;

DG-MOSFET; DRAIN INDUCED BARRIER LOWERING (DIBL); HETERO-MATERIAL GATE;

MOSFET DEVICES;

EID: 1842865585     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2003.12.009     Document Type: Article

References (11)

1. Balestra F., Cristoloveanu S., Benachir M., Brini J., Elewa T. Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance. IEEE Electron Dev. Lett. 8:1987;410-412.
2. Long W., Ou H., Kuo J.M., Chen K.K. Dual Material Gate (DMG) field effect transistor. IEEE Trans. Electron Dev. 46:1999;865-870.
3. Saxena M., Haldar S., Gupta M., Gupta R.S. Physics based analytical modeling of potential and electrical field distribution in dual material gate (DMG)-MOSFET for improved hot electron effect and carrier transport efficiency. IEEE Trans. Electron Dev. 49:2002;1928-1938.
4. Saxena M., Haldar S., Gupta M., Gupta R.S. Physics based modeling and simulation of dual material gate stack (DUMGAS) MOSFET. Electron. Lett. 39(9th January):2003;155-157.
5. Taur Y. An analytical solution to a double-gate MOSFET with undoped body. IEEE Electron Dev. Lett. 21:2000;245-247.
6. + double-gate SOI MOSFETs IEEE Electron Dev. Lett. 15:1994;386-388.
7. + double-gate SOI MOSFET's. IEEE Trans. Electron Dev. 42:1995;1940-1948.
8. + Double-gate SOI MOSFET's. IEEE Trans. Electron Dev. 43:1996;732-738.
9. Arora N. MOSFET models for VLSI circuit simulation. 1993;Springer-Verlag.
10. SILVACO International, ATLAS: 2D Device Simulator.
11. Hisamoto D. FD/DG-SOI MOSFET - a viable approach to overcoming the device scaling limit. IEDM Tech Dig. 2001;429-432.