Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2009, Pages 191-196

  Jiang, Li ^a,b   Xu, Qiang ^a,b   Chakrabarty, Krishnendu ^c   Mak, T M ^d  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^b SHENZHEN INSTITUTES OF ADVANCED TECHNOLOGY   (China)

^c DUKE UNIVERSITY   (United States)

^d INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; SYSTEM-ON-CHIP; TESTING;

3D TECHNOLOGY; CORE BASED SYSTEM ON CHIPS; PIN COUNTS; ROUTING COSTS; SILICON AREA; TEST ACCESS MECHANISM; TEST ARCHITECTURE; THREE DIMENSIONAL (3D) INTEGRATION;

INTEGRATED CIRCUIT DESIGN;

EID: 76349088251     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1687399.1687434     Document Type: Conference Paper

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