TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC

Proceedings - Design Automation Conference

Volumn , Issue , 2011, Pages 188-193

  Jung, Moongon ^a   Mitra, Joydeep ^b   Pan, David Z ^b   Lim, Sung Kyu ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

3D IC; mechanical reliability; stress; TSV

Indexed keywords

COMPUTER AIDED DESIGN; INTEGRATED CIRCUIT DESIGN; RELIABILITY ANALYSIS; STRESSES; TIMING CIRCUITS;

DESIGN OPTIMIZATION; LINEAR SUPERPOSITION PRINCIPLES; LINEAR SUPERPOSITIONS; MECHANICAL RELIABILITY; MECHANICAL RELIABILITY ANALYSIS; STRESS SIMULATIONS; THERMO-MECHANICAL STRESS; VON MISES YIELD CRITERION;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 80052655341     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2024724.2024767     Document Type: Conference Paper

References (8)

1. Geert Van der Plas et al. Design Issues and Considerations for Low-Cost 3D TSV IC Technology. In IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2010.
2. Aditya P. Karmarkar, Xiaopeng Xu, and Victor Moroz. Performance and Reliability Analysis of 3D-Integration Structures Employing Through Silicon Via (TSV. In IEEE Int. Reliability Physics Symposium, 2009.
3. Dae Hyun Kim, Krit Athikulwongse, and Sung Kyu Lim. A Study of Through-Silicon-Via Impact on the 3D Stacked IC Layout. In Proc. IEEE Int. Conf. on Computer-Aided Design, 2009.
4. Xi Liu, Qiao Chen, Pradeep Dixit, Ritwik Chatterjee, Rao R. Tummala, and Suresh K. Sitaraman. Failure Mechanisms and Optimum Design for Electroplated Copper Through-Silicon Vias (TSV). In IEEE Electronic Components and Technology Conf., 2009.
5. Kuan H. Lu, Xuefeng Zhang, Suk-Kyu Ryu, Jay Im, Rui Huang, and Paul S. Ho. Thermo-mechanical reliability of 3-D ICs containing through silicon vias. In IEEE Electronic Components and Technology Conf., 2009.
6. Suk-Kyu Ryu, Kuan-Hsun Lu, Xuefeng Zhang, Jang-Hi Im, Paul S. Ho, and Rui Huang. Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon-Vias for 3-D Interconnects. In IEEE Trans. on Device and Material Reliability, 2010.
7. Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, and David Z. Pan. TSV Stress Aware Timing Analysis with Applications to 3D-IC Layout Optimization. In Proc. ACM Design Automation Conf., 2010.
8. Jing Zhang, Max O. Bloomfield, Jian-Qiang Lu, Ronald J. Gutmann, and Timothy S. Cale. Modeling Thermal Stresses in 3-D IC Interwafer Interconnects. In IEEE Trans. on Semiconductor Manufacturing, 2006.