Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2010, Pages

  Healy, Michael B ^a   Athikulwongse, Krit ^a   Goel, Rohan ^a   Hossain, Mohammad M ^a   Kim, Dae Hyun ^a   Lee, Young Joon ^a   Lewis, Dean L ^a   Lin, Tzu Wei ^a   Liu, Chang ^a   Jung, Moongon ^a   Ouellette, Brian ^a   Pathak, Mohit ^a   Sane, Hemant ^a   Shen, Guanhao ^a   Woo, Dong Hyuk ^a   Zhao, Xin ^a   Loh, Gabriel H ^b   Lee, Hsien Hsin S ^a   Lim, Sung Kyu ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b School of Chemistry and Biochemistry   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3D PROCESSORS; 3D STACKING TECHNOLOGY; 3D-STACKED MEMORY; DESIGN AND ANALYSIS; DESIGN FLOWS; MANY-CORE; MEMORY BANDWIDTHS;

DESIGN; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; OPTICAL PROJECTORS;

THREE DIMENSIONAL;

EID: 78649888644     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2010.5617464     Document Type: Conference Paper

References (4)

1. K. N. et al. An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. In IEEE Int. Solid-State Circuits Conf., pages 480-481,481a, feb. 2009.
2. U. K. et al. 8Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology. IEEE Journal of Solid-State Circuits, 45(1):111-119, jan. 2010.
3. T. Thorolfsson, K. Gonsalves, and P. Franzon. Design automation for a 3dic fft processor for synthetic aperture radar: A case study. In Proc. ACM Design Automation Conf., pages 51-56, 2009.
4. D. H. Woo and H.-H. S. Lee. Extending Amdahl's Law for Energy-Efficient Computing in the Many-Core Era. IEEE Computer, 41(12):24-31, 2008.