Layout effects in fine grain 3D integrated regular microprocessor blocks

Proceedings - Design Automation Conference

Volumn , Issue , 2011, Pages 639-644

  Nandakumar, Vivek S ^a   Marek Sadowska, Malgorzata ^a  

^a University of California   (United States)

Author keywords

3D ICs; 3D layouts; SRAM register partitioning; TSV limitations

Indexed keywords

COMPUTER AIDED DESIGN; DETERIORATION; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT LAYOUT;

3-D ICS; 3D LAYOUTS; ARCHITECTURAL SOLUTIONS; CIRCUIT ELEMENTS; LAYOUT MODIFICATION; PERFORMANCE DETERIORATION; THROUGH SILICON VIAS; TSV LIMITATIONS;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 80052654375     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2024724.2024871     Document Type: Conference Paper

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