Whitespace redistribution for thermal via insertion in 3D stacked ICs

2007 IEEE International Conference on Computer Design, ICCD 2007

Volumn , Issue , 2007, Pages 267-272

  Wong, Eric ^a   Lim, Sung Kyu ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; COMPUTER DESIGNS; DEVICE LAYERS; HEAT DISSIPATION; IC DESIGNS; INTERNATIONAL CONFERENCES;

COMPUTATIONAL FLUID DYNAMICS;

EID: 52949111338     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2007.4601912     Document Type: Conference Paper

References (8)

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3. Z. Li, X. Hong, Q. Zhao, S. Zeng, J. Bian, H. Yang, and C. K. Cheng, "Integrating dynamic thermal via planning with 3d floorplanning algorithm," in Proc. Int. Symp. on Physical Design, 2006.
4. E. Wong and S. K. Lim, "3d floorplanning with thermal vias," in Proc. Design, Automation and Test in Europe, 2006, pp. 878-883.
5. B. Goplen and S. Sapatnekar, "Thermal Via Placement in 3-D ICs," in Proc. Int. Symp. on Physical Design, 2005.
6. X. Tang, R. Tian, and D. F. Wong, "Optimal redistribution of white space for wire length minimization," in Proc. Asia and South Pacific Design Automation Conf., 2005, pp. 412-417.
7. H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "Rectangle packing based module placement," in Proc. IEEE Int. Conf. on Computer-Aided Design, 1995, pp. 472-479.
8. J. Cong, J. Wei, and Y. Zhang, "A Thermal-Driven Floorplanning Algorithm for 3D ICs," in Proc. IEEE Int. Conf. on Computer-Aided Design, 2004.