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Volumn , Issue , 2009, Pages 347-352

A novel thermal optimization flow using incremental floor planning for 3D ICs

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; 3D IC DESIGNS; CRITICAL CHALLENGES; FLOOR-PLANNING; FLOORPLAN; HOT BLOCKS; HOT SPOTS; INCREMENTAL CHANGES; MIXED INTEGER LINEAR PROGRAMMING MODELS; MULTIPLE OBJECTIVES; ON-CHIP TEMPERATURES; RUN-TIME; THERMAL OPTIMIZATIONS; WIRE LENGTHS;

EID: 64549085333     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2009.4796505     Document Type: Conference Paper
Times cited : (30)

References (20)
  • 1
    • 16244385917 scopus 로고    scopus 로고
    • A Thermal-Driven Floorplanning Algorithm for 3D ICs
    • J.Cong, J. Wei and Y. Zhang, "A Thermal-Driven Floorplanning Algorithm for 3D ICs", in Procceedings of ICCAD, 2004
    • (2004) Procceedings of ICCAD
    • Cong, J.1    Wei, J.2    Zhang, Y.3
  • 5
    • 0032681930 scopus 로고    scopus 로고
    • Standard cell placement for even on-chip thermal distribution
    • C.H. Tsai and S.M.S Kang, "Standard cell placement for even on-chip thermal distribution", in Procceedings of ISPD, 1999
    • (1999) Procceedings of ISPD
    • Tsai, C.H.1    Kang, S.M.S.2
  • 7
    • 1542269347 scopus 로고    scopus 로고
    • Reducing power density through activity migration
    • Aug
    • S. Heo, K. Barr and K. Asanovic, "Reducing power density through activity migration", in Procceedings of ISLPED, Aug., 2003.
    • (2003) Procceedings of ISLPED
    • Heo, S.1    Barr, K.2    Asanovic, K.3
  • 8
    • 33847382055 scopus 로고    scopus 로고
    • Evaluation of Thermal-aware design Techniques for Microprocessors
    • T.D. Richardson and Y. Xie, "Evaluation of Thermal-aware design Techniques for Microprocessors", in Proceedings of ASICON, 2005.
    • (2005) Proceedings of ASICON
    • Richardson, T.D.1    Xie, Y.2
  • 11
    • 23044526631 scopus 로고    scopus 로고
    • Constrained Polygon Transformations for Incremental Floorplanning
    • July
    • S. Liao, M.A. Lopez and D. Mehta, "Constrained Polygon Transformations for Incremental Floorplanning", ACM Trans. On DAES, Vol.6, No.3, July 2001.
    • (2001) ACM Trans. On DAES , vol.6 , Issue.3
    • Liao, S.1    Lopez, M.A.2    Mehta, D.3
  • 16
    • 64549128017 scopus 로고    scopus 로고
    • www.gnu.org/software/glpk/
  • 18
    • 0742321357 scopus 로고    scopus 로고
    • Fixed-outline Floorplanning: Enabling Hierarchical Design
    • Dec
    • S.N. Adya, I.L. Markov, "Fixed-outline Floorplanning: Enabling Hierarchical Design", IEEE Trans. On VLSI systems, Vol.11,No.1, pp.1120-1135, Dec.2003.
    • (2003) IEEE Trans. On VLSI systems , vol.11 , Issue.1 , pp. 1120-1135
    • Adya, S.N.1    Markov, I.L.2
  • 19
    • 0033684694 scopus 로고    scopus 로고
    • Floorplan Sizing By linear Programming Approximation
    • P. Chen and E.S. Kuh, "Floorplan Sizing By linear Programming Approximation", in Proceedings of DAC, 2000
    • (2000) Proceedings of DAC
    • Chen, P.1    Kuh, E.S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.