메뉴 건너뛰기




Volumn 2006, Issue , 2006, Pages 178-185

Integrating dynamic thermal via planning with 3D floorplanning algorithm

Author keywords

3D Floorplanning; Thermal Optimization; Thermal Via

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; OPTIMIZATION; PROBLEM SOLVING; STRATEGIC PLANNING;

EID: 33745958184     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1123008.1123048     Document Type: Conference Paper
Times cited : (45)

References (16)
  • 2
    • 33747566850 scopus 로고    scopus 로고
    • 3D-ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems on chip integration
    • K. Banerjee, S.J. Souri, P. Kapur, K.C. Saraswat, "3D-ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems on Chip Integration", Proceedings of the IEEE, Vol. 89, No.5, 2001, pp. 602-633.
    • (2001) Proceedings of the IEEE , vol.89 , Issue.5 , pp. 602-633
    • Banerjee, K.1    Souri, S.J.2    Kapur, P.3    Saraswat, K.C.4
  • 3
    • 0035715858 scopus 로고    scopus 로고
    • Thermal analysis of heterogeneous 3D ICs with various integration scenarios
    • T. Y. Chiang, S.J. Souri, C.O. Chui, and K.C. Saraswat, "Thermal Analysis of Heterogeneous 3D ICs with Various Integration Scenarios," Tech. Dig. IEDM, pp. 681-684, 2001
    • (2001) Tech. Dig. IEDM , pp. 681-684
    • Chiang, T.Y.1    Souri, S.J.2    Chui, C.O.3    Saraswat, K.C.4
  • 5
    • 16244385917 scopus 로고    scopus 로고
    • A thermal-driven floorplanning algorithm for 3D ICs
    • J. Cong, J. Wei, and Y. Zhang, "A Thermal-Driven Floorplanning Algorithm for 3D ICs", Proc. ICCAD, 2004
    • (2004) Proc. ICCAD
    • Cong, J.1    Wei, J.2    Zhang, Y.3
  • 7
    • 0347409236 scopus 로고    scopus 로고
    • Efficient thermal placement of standard cells in 3D ICs using a force directed approach
    • Nov.
    • B. Goplen and S. Sapatnekar, "Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach", Proc. ICCAD, Nov. 2003.
    • (2003) Proc. ICCAD
    • Goplen, B.1    Sapatnekar, S.2
  • 10
    • 33745949868 scopus 로고    scopus 로고
    • Performance, and computer aided design of three dimensional integrated circuits
    • S. Das, et al. "Performance, and Computer Aided Design of Three Dimensional Integrated Circuits", Proc. International Symposium on Physical Design, 2004
    • (2004) Proc. International Symposium on Physical Design
    • Das, S.1
  • 11
    • 84861422150 scopus 로고    scopus 로고
    • Thermal-driven multilevel routing for 3-D 1Cs
    • Jan.
    • J. Congand Y. Zhang, "Thermal-Driven Multilevel Routing for 3-D 1Cs," Proc. ASP-DAC, pp 121-126, Jan.2005.
    • (2005) Proc. ASP-DAC , pp. 121-126
    • Congand, J.1    Zhang, Y.2
  • 12
    • 0035208728 scopus 로고    scopus 로고
    • Compact modeling and SPICE-based simulation for electrothermal analysis of multilevel ULSI interconnects
    • T.Y. Chiang, K. Banerjee, and K.C. Saraswat. "Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects," Proc. ICCAD, 2001.
    • (2001) Proc. ICCAD
    • Chiang, T.Y.1    Banerjee, K.2    Saraswat, K.C.3
  • 14
    • 33751410351 scopus 로고    scopus 로고
    • Thermal via planning for 3D ICs
    • Nov.
    • J. Cong and Y. Zhang, "Thermal Via Planning for 3D ICs", Proc. ICCAD, Nov.2005.
    • (2005) Proc. ICCAD
    • Cong, J.1    Zhang, Y.2
  • 15
    • 0034481271 scopus 로고    scopus 로고
    • Corner Block List: An effective and efficient topological representation of non-slicing floorplan
    • Nov.
    • X.L. Hong, G. Huang, Y. Cai, J. Gu, S. Dong, C.-K. Cheng, and J. Gu, "Corner Block List: An effective and efficient topological representation of non-slicing floorplan," Proc. ICCAD, pp. 8-12, Nov. 2000.
    • (2000) Proc. ICCAD , pp. 8-12
    • Hong, X.L.1    Huang, G.2    Cai, Y.3    Gu, J.4    Dong, S.5    Cheng, C.-K.6    Gu, J.7
  • 16
    • 54549110399 scopus 로고    scopus 로고
    • Optimal redistribution of white space for wire length minimization
    • Jan.
    • X. Tang, R. Tian and D.F. Wong, "Optimal Redistribution of White Space for Wire Length Minimization," Proc. ASP-DAC, pp.412-417, Jan.2006
    • (2006) Proc. ASP-DAC , pp. 412-417
    • Tang, X.1    Tian, R.2    Wong, D.F.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.