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Volumn , Issue , 2009, Pages 77-84

From 3D circuit technologies and data structures to interconnect prediction

Author keywords

3D floorplanning; 3D integration; Data structures; Interconnect prediction; Three dimensional circuits

Indexed keywords

3-D INTEGRATED CIRCUIT; 3-D INTEGRATION; 3-D PACKAGES; 3D CIRCUIT; 3D DATA; 3D TECHNOLOGY; FLOOR-PLANNING; HETEROGENEOUS SYSTEMS; INTEGRATION DENSITY; INTERCONNECT PREDICTION; LAYOUT DESIGNERS; MOORE'S LAW; NEW TECHNOLOGIES; RAPID DEVELOPMENT; THREE-DIMENSIONAL CIRCUITS;

EID: 77950825018     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1572471.1572485     Document Type: Conference Paper
Times cited : (21)

References (24)
  • 1
    • 77950849229 scopus 로고    scopus 로고
    • tech. rep., ESIA, JEITA, KSIA, TSIA and SIA
    • ITRS, "http://www.itrs.net/reports.html," tech. rep., ESIA, JEITA, KSIA, TSIA and SIA, 2007.
    • (2007)
  • 4
    • 4544359901 scopus 로고    scopus 로고
    • SOP: What is it and why? A new microsystem-integration technology paradigm-moore's law for system integration of miniaturized convergent systems of the next decade
    • May
    • R. Tummala, "SOP: What is it and why? A new microsystem-integration technology paradigm-moore's law for system integration of miniaturized convergent systems of the next decade," Advanced Packaging, IEEE Transactions on, vol.27, pp. 241-249, May 2004.
    • (2004) Advanced Packaging, IEEE Transactions on , vol.27 , pp. 241-249
    • Tummala, R.1
  • 5
    • 28344435928 scopus 로고    scopus 로고
    • Physical design for 3D system on package
    • Nov.-Dec.
    • S. Lim, "Physical design for 3D system on package," Design & Test of Computers, IEEE, vol.22, pp. 532-539, Nov.-Dec. 2005.
    • (2005) Design & Test of Computers, IEEE , vol.22 , pp. 532-539
    • Lim, S.1
  • 6
    • 0036928172 scopus 로고    scopus 로고
    • Electrical integrity of state-of-the-art 0.13 m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication
    • K. W. Guarini, A. W. Topol, M. Ieong et. al, "Electrical integrity of state-of-the-art 0.13 m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication," in Proc. Digest. International Electron Devices Meeting IEDM '02, pp. 943-945, 2002.
    • (2002) Proc. Digest. International Electron Devices Meeting IEDM '02 , pp. 943-945
    • Guarini, K.W.1    Topol, A.W.2    Ieong, M.3
  • 9
    • 34548359365 scopus 로고    scopus 로고
    • Processor design in 3D die-stacking technologies
    • May-June
    • G. H. Loh, Y. Xie, and B. Black, "Processor design in 3D die-stacking technologies," Micro, IEEE, vol.27, pp. 31-48, May-June 2007.
    • (2007) Micro, IEEE , vol.27 , pp. 31-48
    • Loh, G.H.1    Xie, Y.2    Black, B.3
  • 16
    • 27144447049 scopus 로고    scopus 로고
    • Three dimensional module packing by simulated annealing
    • 2-5 Sept.
    • H. Ninomiya and H. Asai, "Three dimensional module packing by simulated annealing," in Evolutionary Computation, IEEE Congress on, vol.2, pp. 1069-1074, 2-5 Sept. 2005.
    • (2005) Evolutionary Computation, IEEE Congress on , vol.2 , pp. 1069-1074
    • Ninomiya, H.1    Asai, H.2
  • 21
    • 0015206785 scopus 로고
    • On a pin versus block relationship for partitions of logic graphs
    • B. S. Landman and R. L. Russo, "On a pin versus block relationship for partitions of logic graphs," Computers, IEEE Transactions on, vol.C-20, no.12, pp. 1469-1479, 1971.
    • (1971) Computers, IEEE Transactions on , vol.C-20 , Issue.12 , pp. 1469-1479
    • Landman, B.S.1    Russo, R.L.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.