TSV redundancy: Architecture and design issues in 3D IC

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2010, Pages 166-171

  Hsieh, Ang Chih ^a   Hwang, Tingting ^a   Chang, Ming Tung ^b   Tsai, Min Hsiu ^b   Tseng, Chih Mou ^b   Li, Hung Chun ^b  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b Global Unichip   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; 3-D INTEGRATION; 3D TECHNOLOGY; COMMUNICATION LINKS; COST OF MANUFACTURING; CRITICAL DESIGN; DESIGN ISSUES; HIGH DENSITY; LOW POWER; PROBABILISTIC MODELS; RECOVERY RATE; THROUGH-SILICON-VIA; TIMING PROBLEM; VERTICAL DIRECTION;

COST REDUCTION; DIES; THREE DIMENSIONAL;

DESIGN;

EID: 77953096507     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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