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Volumn , Issue , 2011, Pages 42-49

Signal integrity analysis and optimization for 3D ICs

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; ANALYSIS RESULTS; CHIP AREAS; CRITICAL PATH DELAYS; FORCE-DIRECTED; SIGNAL INTEGRITY; SIGNAL INTEGRITY ANALYSIS;

EID: 79959237959     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2011.5770701     Document Type: Conference Paper
Times cited : (15)

References (10)
  • 4
    • 77950935728 scopus 로고    scopus 로고
    • Modeling and analysis of coupling between tsvs, metal, and rdl interconnects in TSV-based 3D IC with silicon interposer
    • K. Yoon, G. Kim, W. Lee, T. Song, J. Lee, H. Lee, K. Park, and J. Kim, Modeling and Analysis of Coupling between TSVs, Metal, and RDL interconnects in TSV-based 3D IC with Silicon Interposer in Electronics Packaging Technology Conference, 2009, pp. 702-706.
    • (2009) Electronics Packaging Technology Conference , pp. 702-706
    • Yoon, K.1    Kim, G.2    Lee, W.3    Song, T.4    Lee, J.5    Lee, H.6    Park, K.7    Kim, J.8
  • 6
    • 69549108427 scopus 로고    scopus 로고
    • Closed-form expressions of 3-D via resistance, inductance, and capacitance
    • I. Savidis and E. G. Friedman, Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance," in IEEE Trans. on Electron Devices, 2009, pp. 1873-1881.
    • (2009) IEEE Trans. on Electron Devices , pp. 1873-1881
    • Savidis, I.1    Friedman, E.G.2
  • 7
  • 9
    • 70549084860 scopus 로고    scopus 로고
    • Through-slicon via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs
    • N. H. Khan, S. M. Alam, and S. Hassoun, Through-Slicon Via (TSV)-induced Noise Characterization and Noise Mitigation using Coaxial TSVs in IEEE International 3D System Integration Conf., 2009, pp. 1-7.
    • (2009) IEEE International 3D System Integration Conf. , pp. 1-7
    • Khan, N.H.1    Alam, S.M.2    Hassoun, S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.