Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration

ACM Transactions on Design Automation of Electronic Systems

Volumn 11, Issue 2, 2006, Pages 325-345

  Li, Zuoyuan ^a   Hong, Xianlong ^a   Zhou, Qiang ^a   Bian, Jinian ^a   Yang, Hannah H ^b   Pitchumani, Vijay ^b  

^a TSINGHUA UNIVERSITY   (China)

^b INTEL CORPORATION   (United States)

Author keywords

3D IC; Floorplanning; Thermal

Indexed keywords

EID: 33746059766     PISSN: 10844309     EISSN: 10844309     Source Type: Journal    
DOI: 10.1145/1142155.1142159     Document Type: Review

References (21)

1. ALSARAWI, S. F., ABBOTT, D., AND FRANZON, P. D. 1998. A review of 3-D packaging technology. IEEE Trans. Compon. Packag. Manufact. Tech. Part B 21, 1(Jan.), 2-14.
2. BANERJEE, K., SOURI, S. J., KAPUR, P., AND SARASWAT, K. C. 2001. 3D-ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems on chip integration. Proc. IEEE 89, 5(May), 602-633.
3. BAZARGAN, K., KASTNER, R., AND SARRAFZADEH, M. 1999. 3D floorplanning: Simulated annealing and greedy placement methods for reconfigurable computing systems. In Proceedings of the 10th IEEE International Workshop on Rapid System Prototyping. 38-43.
4. CHEN, G. AND SAPATNEKAR, S. 2003. Partition-driven standard cell thermal placement. In Proceedings of the 2003 ACM International Symposium on Physical Design. Vol. 1. 75-80.
5. CHENG, L., DENG, L., AND WONG D. F. 2005. Floorplanning for 3D VLSI design. In Proceedings of the 2005 ACM/IEEE Asia and South Pacific Design Automation Conference. 405-411.
6. CHU, C. N. AND WONG, D. F. 1997. A matrix synthesis approach to thermal placement. In Proceedings of the 1997 ACM International Symposium on Physical Design. 163-168.
7. CONG, J. AND ZHANG, Y. 2005. Thermal-driven multilevel routing for 3-D ICs. In Proceedings of the 2005 ACM / IEEE Asia and South Pacific Design Automation Conference. 121-126.
8. CONG, J., WEI, J., AND ZHANG, Y. 2004. A thermal-driven floorplanning algorithm for 3D ICs. In Proceedings of the 2004 ACM / IEEE International Conference on Computer Aided Design. 306-313.
9. DAS, S., FAN, A., AND CHEN, K. N. 2004. Technology, performance, and computer-aided design of three-dimensional integrated circuits. In Proceedings of the 2004 ACM International Symposium on Physical Design. 108-115.
10. DENG, Y. AND MALY, W. P. 2001. Interconnect characteristics of 2.5-D system integration scheme. In Proceedings of the 2001 ACM International Symposium on Physical Design. 171-175.
11. EISENMANN, H. AND JOHANNES, F. M. 1998. Generic global placement and floorplanning. In Proceedings of the 1998 ACM/IEEE Design Automation Conference. 269-274.
12. GOPLEN, B. AND SAPATNEKAR, S. 2003. Efficient thermal placement of standard cells in 3D ICs using a force directed approach. In Proceedings of the 2003 ACM / IEEE International Conference on Computer Aided Design. 86-89.
13. GOPLEN, B. AND SAPATNEKAR, S. 2005. Thermal via placement in 3D ICs. In Proceedings of the 2005 ACM International Symposium on Physical Design. 167-174.
14. HONG, X. L., HUANG, G., CAI, Y., Gu, J., DONG, S., CHENG, C. K., AND Gu, J. 2000. Corner block list: An effective and efficient topological representation of non-slicing floorplan. In Proceedings of the 2000 ACM/IEEE International Conference on Computer Aided Design. 8-12.
15. LALL, B., ORTEGA, A., AND KABIR, H. 1994. Thermal design rules for electronic components on conducting boards in passively cooled enclosures. In Proceedings of the 1994 Inter-Society Conference on Thermal Phenomena. 50-61.
16. Li, Z., HONG, X. L., ZHOU, Q., CAI, Y., BIAN, J., YANG, H., SAXENA, P., AND PITCHUMANI, V. 2005. A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. In Proceedings of the 2005 IEEE International Symposium on Circuits and Systems. Vol. 6. 280-233.
17. Lou, J., THAKUR, S., KRISHNAMOORTHY, S., AND SHENG, H. S. 2002. Estimating routing congestion using probabilistic analysis. IEEE Trans. Comput. Aid. Des. 21, 1(Jan.), 32-41.
18. SHIU, P. H., RAVICHANDBAN, R., EASWAR, S., AND LIM, S. K. 2004. Multi-layer floorplanning for reliable sytem-on-package. In Proceedings of the 2004 IEEE International Symposium on Circuits and Systems. Vol. 5. 69-72.
19. TSAI, C. H. AND KANG, S. M. 2000. Cell-level placement for improving substrate thermal distribution. IEEE Trans. Comput. Aid. Des. 19, 2(Feb.), 253-266.
20. WANG, T. Y., LEE, Y. M., AND CHEN, C. P. 2003. 3D-thermal-ADI: Efficient chip-level transient thermal simulator. In Proceedings of the 2003 ACM International Symposium on Physical Design, 10-17.
21. YAMAZAKI, H., SAKANUSHI, K., NAKATAKE, S., AND KAJITANI, Y. 2000. The SD-packing by meta data structure and packing heuristics. IEICE Trans. Fundament. Electron. Commun. Comput. Sci. E83-A, 4(Apr.), 639-645.