Low-power and reliable clock network design for through-silicon via (TSV) based 3D ICs

IEEE Transactions on Components, Packaging and Manufacturing Technology

Volumn 1, Issue 2, 2011, Pages 247-259

  Zhao, Xin ^a   Minz, Jacob ^b   Lim, Sung Kyu ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

3D clock network; clock slew; low power 3D IC design; through silicon via (TSV)

Indexed keywords

3D IC DESIGN; CLOCK NETWORK; CLOCK POWER CONSUMPTION; CLOCK SLEW; CLOCK TREE SYNTHESIS; RESISTANCE CAPACITANCE; THREE-DIMENSIONAL METHOD; THROUGH-SILICON VIA;

ALGORITHMS; CAPACITANCE; CLOCK DISTRIBUTION NETWORKS; DESIGN; ELECTRIC CLOCKS; FORESTRY; LOW POWER ELECTRONICS; MICROPROCESSOR CHIPS; SPICE; THREE DIMENSIONAL; TREES (MATHEMATICS);

THREE DIMENSIONAL COMPUTER GRAPHICS;

CLOCKS; ELECTRIC CIRCUITS; ELECTRONICS; FORESTRY; MICROPROCESSORS; SILICON; THREE DIMENSIONAL DESIGN;

EID: 80053645511     PISSN: 21563950     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCPMT.2010.2099590     Document Type: Article

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