Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs

International Workshop on System Level Interconnect Prediction, SLIP

Volumn , Issue , 2009, Pages 85-92

  Kim, Dae Hyun ^a   Mukhopadhyay, Saibal ^a   Lim, Sung Kyu ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

3D IC; Interconnect prediction; Rent's rule; Through silicon via; TSV; Wirelength distribution

Indexed keywords

3-D ICS; 3-D INTEGRATED CIRCUIT; DESIGN DECISIONS; DESIGN PARAMETERS; IC INTERCONNECT; INTERCONNECT PREDICTION; MANUFACTURING COST; POWER OVERHEAD; PREDICTION MODEL; RENT'S RULE; SILICON AREA; THROUGH SILICON VIAS; THROUGH-SILICON-VIA; WIRE LENGTH; WIRELENGTH DISTRIBUTION;

ELECTRIC POWER SYSTEM INTERCONNECTION; ELECTRONICS PACKAGING; FORECASTING; INFRARED DETECTORS; MATHEMATICAL MODELS; TECHNICAL PRESENTATIONS;

THREE DIMENSIONAL;

EID: 77950787864     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1572471.1572486     Document Type: Conference Paper

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