On-chip tensile testing of nanoscale silicon free-standing beams

Journal of Materials Research

Volumn 27, Issue 3, 2012, Pages 571-579

  Bhaskar, Umesh ^a   Passi, Vikram ^a   Houri, Samer ^a   Escobedo Cousin, Enrique ^b   Olsen, Sarah H ^b   Pardoen, Thomas ^a   Raskin, Jean Pierre ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

^b NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

Microelectromechanical; Nanoscale; Si

Indexed keywords

ATOMIC ARRANGEMENT; ATOMIC FORCE; CHARACTERIZATION TECHNIQUES; DEFECT-FREE; FRACTURE STRAIN; FREE-STANDING BEAMS; LAB-ON-CHIP; LARGE DEFORMATIONS; LARGE STRAINS; MECHANICAL BEHAVIOR; MICRO-ELECTRO-MECHANICAL; MONOCRYSTALLINE; NANO SCALE; NANO-METER SCALE; NANOMECHANICAL TESTING; ON CHIPS; PROOF OF CONCEPT; SCALE EFFECTS; SILICON BEAMS; SILICON ON INSULATOR WAFERS; SURFACE INSTABILITY; TEST SPECIMENS; TRANSPORT CHARACTERISTICS; TRANSPORT MEASUREMENTS;

ATOMIC FORCE MICROSCOPY; CHARACTERIZATION; DEFORMATION; MONOCRYSTALLINE SILICON; NANOTECHNOLOGY; PHOSPHORUS; SEMICONDUCTING SILICON COMPOUNDS; SILICON; STRAIN; SURFACE DEFECTS; SURFACE ROUGHNESS; TENSILE TESTING;

SILICON WAFERS;

EID: 84856429960     PISSN: 08842914     EISSN: 20445326     Source Type: Journal    
DOI: 10.1557/jmr.2011.340     Document Type: Article

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