Strained p-channel FinFETs with extended Π-shaped silicon-germanium source and drain stressors

IEEE Electron Device Letters

Volumn 28, Issue 10, 2007, Pages 905-908

  Tan, Kian Ming ^a   Liow, Tsung Yang ^a   Lee, Rinus T P ^a   Hoe, Keat Mun ^b   Tung, Chih Hang ^b   Balasubramanian, N ^b   Samudra, Ganesh S ^a   Yeo, Yee Chia ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

Extended II; FinFET; Multiple gate; SiGe; Source drain stressors; Strain; Stress

Indexed keywords

COMPRESSIVE STRESS; COMPUTER SIMULATION; GATES (TRANSISTOR); SEMICONDUCTING SILICON COMPOUNDS; STRAIN;

FIN FIELD-EFFECT TRANSISTOR (FINFET); MULTIPLE GATE; SOURCE/DRAIN STRESSORS;

FIELD EFFECT TRANSISTORS;

EID: 34948892865     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.905406     Document Type: Article

References (10)

1. 0.2 in the source and drain regions," in Symp. VLSI Tech., 2005, pp. 194-195.
2. T.-Y. Liow, K.-M. Tan, R. T. P. Lee, A. Du, C.-H. Tung, G. S. Samudra, W.-J. Yoo, N. Balasubramanian, and Y.-C. Yeo, "Strained n-channel FinFETs with 25 nm gate length and silicon-carbon source/drain regions for performance enhancement," in Symp. VLSI Tech., 2006, pp. 56-57.
3. J. Kavalieros, B. Doyle, S. Datta, G. Dewey, M. Doczy, B. Jin, D. Lionberger, M. Metz, W. Rachmady, M. Radosavljevic, U. Shah, N. Zelick, and R. Chau, "Tri-gate transistor architecture with high-k gate dielectrics, metal gates, and strain engineering," in Symp. VLSI Tech., 2006, pp. 50-51.
4. Z. Krivokapic, C. Tabery, W. Maszara, Q. Xiang, and M.-R. Lin, "High performance 45 nm CMOS technology with 20 nm multi-gate devices," in Proc. SSDM, 2003, pp. 760-761.
5. W. Xiong, K. Shin, C. R. Cleavelin, T. Schulz, K. Schruefer, I. Cayrefourcq, M. Kennard, C. Mazure, P. Patruno, and T.-J. K. Liu, "FinFET performance enhancement with tensile metal gates and strained silicon on insulator (sSOI) substrate," in DRC, 2006, pp. 39-40.
6. C. Y. Kang, R. Choi, S. C. Song, B. S. Ju, M. M. Hussain, B. H. Lee, J.-W. Yang, P. Zeitzoff, D. Pham, W. Xiong, and H.-H. Tseng, "Effects of ALD TiN metal gate thickness on metal gate/high-k dielectric SOI FinFET characteristics," in IEEE Int. SOI Conf. Proc., 2006, pp. 135-136.
7. K.-M. Tan, T.-Y. Liow, R. T. P. Lee, C.-H. Tung, N. Balasubramanian, G. S. Samudra, W.-J. Yoo, and Y.-C. Yeo, "Drive current enhancement in FinFETs using gate-induced stress," IEEE Electron Device Letters, vol. 27, no. 9, pp. 769-771, Sep. 2006.
8. F.-L. Yang, H.-Y. Chen, C.-C. Huang, C.-H. Ge, K.-W. Su, C.-C. Huang, C.-Y. Chang, D.-W. Lin, C.-C. Wu, J.-K. Ho, W.-C. Lee, Y.-C. Yeo, C. H. Diaz, M.-S. Liang, J. Y.-C. Sun, and C. Hu, "Strained FIP-SOI (FinFET/FD/PD-SOI) for sub-65 nm CMOS scaling," in Symp VLSI Tech., 2003, pp. 137-138.
9. N. Collaert, A. De Keersgieter, K. G. Anil, R. Rooyackers, G. Eneman, M. Goodwin, B. Eyckens, E. Sleeckx, J.-F. de Marneffe, K. De Meyer, P. Absil, M. Jurczak, and S. Biesemans, "Performance improvement of tall triple gate devices with strained SiN layers," IEEE Electron Device Letters, vol. 26, no. 11, pp. 820-822, Nov. 2005.
10. W. Xiong, C. Rinn Cleavelin, P. Kohli, C. Huffman, T. Schulz, K. Schruefer, G. Gebara, K. Mathews, P. Patruno, Y.-M. Le Vaillant, I. Cayrefourcq, M. Kennard, C. Mazure, K. Shin, and T.-J. K. Liu, "Impact of strained-silicon-on-insulator (sSOI) substrate on FinFET mobility," IEEE Electron Device Letters, vol. 27, no. 7, pp. 612-614, Jul. 2006.