Predictive 3-D modeling of parasitic gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs

IEEE Transactions on Electron Devices

Volumn 58, Issue 10, 2011, Pages 3379-3387

  Zou, Jibin ^a   Xu, Qiumin ^a   Lou, Jieying ^a   Wang, Runsheng ^a   Huang, Ru ^a   Wang, Yangyuan ^a  

^a PEKING UNIVERSITY   (China)

Author keywords

Modeling; parasitic gate capacitance; Schwarz Christoffel mapping; silicon nanowire MOSFETs (SNWTs); source drain extension (SDE)

Indexed keywords

3-D MODELING; 3D ARCHITECTURES; ANALYTICAL MODEL; CAPACITANCE MODEL; CORE MODEL; CYLINDRICAL CHANNEL; DELAY CALCULATION; DESIGN OPTIMIZATION; DEVICE PARAMETERS; EQUIVALENT TRANSFORMATIONS; FRINGE CAPACITANCE; GATE CAPACITANCE; GATE-ALL-AROUND; INTRINSIC CAPACITANCE; OVERLAP CAPACITANCE; PARASITIC CAPACITANCE; SCHWARZ-CHRISTOFFEL MAPPING; SILICON NANOWIRE MOSFETS; SILICON NANOWIRE MOSFETS (SNWTS); SOURCE/DRAIN EXTENSION; SOURCE/DRAIN EXTENSION REGIONS; SURROUNDING-GATE; ULTRA-SMALL;

CAPACITANCE; MATHEMATICAL MODELS; MODELS; NANOWIRES; SEMICONDUCTING SILICON COMPOUNDS; THREE DIMENSIONAL;

MOSFET DEVICES;

EID: 80053205994     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2162521     Document Type: Article

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