Investigation of parasitic effects and design optimization in silicon nanowire MOSFETs for RF applications

IEEE Transactions on Electron Devices

Volumn 55, Issue 8, 2008, Pages 2142-2147

  Zhuge, Jing ^a   Wang, Runsheng ^a   Huang, Ru ^a   Zhang, Xing ^a   Wang, Yangyuan ^a  

^a PEKING UNIVERSITY   (China)

Author keywords

Contact resistance; Parasitic capacitance; RF; Silicon nanowire MOSFETs (SNWTs); Source drain extension (SDE) regions

Indexed keywords

CAPACITANCE; ELECTRIC WIRE; MOSFET DEVICES; NANOSTRUCTURED MATERIALS; NANOSTRUCTURES; NANOWIRES; NONMETALS; SILICON; SILICON CARBIDE; THREE DIMENSIONAL COMPUTER GRAPHICS;

3-D SIMULATIONS; CONTACT RESISTANCE; DESIGN OPTIMIZATION; DEVICE PERFORMANCES; DOMINANT FACTORS; DOPING PROFILES; GA TE LENGTHS; MOSFETS; NANO WIRE STRUCTURES; PARASITIC CAPACITANCE; PARASITIC CAPACITANCES; PARASITIC EFFECTS; RF; RF APPLICATIONS; SERIES RESISTANCE; SILICON CARBIDE DEVICES; SILICON NANOWIRE MOSFETS (SNWTS); SILICON-NANOWIRE; SOURCE/DRAIN EXTENSION; SOURCE/DRAIN EXTENSION (SDE) REGIONS; SOURCE/DRAIN REGIONS;

OPTIMIZATION;

EID: 49249139665     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.926279     Document Type: Article

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