Modeling and significance of fringe capacitance in nonclassical CMOS devices with gate-source/drain underlap

IEEE Transactions on Electron Devices

Volumn 53, Issue 9, 2006, Pages 2143-2149

  Kim, Seung Hwan ^b   Fossum, Jerry G ^a,b   Yang, Ji Woon ^c  

^a IEEE

^b University of Florida   (United States)

^c SEMATECH   (United States)

Author keywords

CMOS speed; Double gate (DG) MOSFET; Fully depleted (FD) silicon on insulator (SOI) MOSFET; MOSFET parasitics

Indexed keywords

CAPACITANCE; GATES (TRANSISTOR); SILICON ON INSULATOR TECHNOLOGY; TWO DIMENSIONAL;

COMPACT MODELS; DOUBLE-GATE (DG) MOSFET DEVICES; FULLY DEPLETED (FD) SILICON-ON-INSULATOR (SOI) MOSFET DEVICES; MOSFET PARASITICS;

CMOS INTEGRATED CIRCUITS;

EID: 33847290671     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.880369     Document Type: Article

References (19)

1. V. Trivedi, J. G. Fossum, and M. M. Chowdhury, "Nanoscale FinFETs with gate-source/drain underlap," IEEE Trans. Electron Devices, vol. 52, no. 1, pp. 56-62, Jan. 2005.
2. J. G. Fossum, M. Chowdhury, V. P. Trivedi, T.-J. King, Y.-K. Choi, J. An, and B. Yu, "Physical insights on design and modeling of nanoscale FinFETs," in IEDM Tech. Dig., Dec. 2003, pp. 679-682.
3. K. Tanaka, K. Takeuchi, and M. Hane, "Practical FinFET design considering GIDL for LSTP (low standby power) devices," in IEDM Tech. Dig., Dec. 2005, pp. 1001-1004.
4. R. S. Shenoy and K. C. Saraswat, "Optimization of extrinsic source/drain resistance in ultrathin body double-gate FETs," IEEE Trans. Nanotechnol., vol. 2, no. 5, pp. 265-270, Dec. 2003.
5. R. Shrivastava and K. Fitzpatrick, "A simple model for the overlap capacitance of a VLSI MOS device," IEEE Trans. Electron Devices, vol. ED-29, no. 12, pp. 1870-1875, Dec. 1982.
6. A. Bansal, B. C. Paul, and K. Roy, "Modeling and optimization of fringe capacitance of nanoscale DGMOS devices," IEEE Trans. Electron Devices, vol. 52, no. 2, pp. 256-262, Feb. 2005.
7. UFDG MOSFET Model User's Guide (Ver. 3.5), SOI Group, Univ. Florida, Gainesville, FL, Feb. 2005. Freescale U.S. Patent Application No. 20060170066.
8. The International Technology Roadmap for Semiconductors, 2003, Austin, TX: Semiconductor Industry Association.
9. MEDICI-4.0 User's Manual, Synopsys, Inc., Durham, NC, 2004.
10. S.-H. Kim and J. G. Fossum, "Nanoscale CMOS: Potential nonclassical technologies versus a hypothetical bulk-silicon technology," Solid Slate Electron., vol. 49, no. 4, pp. 595-605, Apr. 2005.
11. V. P. Trivedi and J. G. Fossum, "Scaling fully depleted SOI CMOS," IEEE Trans. Electron Devices, vol. 50, no. 10, pp. 2095-2103, Oct. 2003.
12. M. Zahn, Electromagnetic Field Tlieory: A Problem Solving Approach. New York: Wiley, 1979, pp. 272-273.
13. J. G. Fossum, V. P. Trivedi, M. M. Chowdhury, S.-H. Kim, and W. Zhang, "Recent upgrades and applications of UFDG," in Proc. Tech. Nanotechnol. Conf. (WCM), May 2006, pp. 674-679.
14. L. Ge and J. G. Fossum, "Analytical modeling of quantization and volume inversion in thin Si-film MOSFETs," IEEE Trans. Electron Devices, vol. 49, no. 2, pp. 287-294, Feb. 2002.
15. S.-H. Kim, J. G. Fossum, and V. P. Trivedi, "Bulk inversion in FinFETs and implied insights on effective gate width," IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 1993-1997, Sep. 2005.
16. L. Ge, J. G. Fossum, and B. Liu, "Physical compact modeling and analysis of velocity overshoot in extremely scaled CMOS devices and circuits," IEEE Trans. Electron Devices, vol. 48, no. 9, pp. 2074-2080, Sep. 2001.
17. X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Sub-50 nm FinFET: PMOS," in IEDM Tech. Dig., Dec. 1999, pp. 67-70.
18. J.-W. Yang and J. G. Fossum, "On the feasibility of nanoscale triple-gate CMOS transistors," IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1159-1164, Jun. 2005.
19. J. G. Fossum, L.-Q. Wang, J.-W. Yang, S.-H. Kim, and V. P. Trivedi, "Pragmatic design of nanoscale multi-gate CMOS," in IEDM Tech. Dig., Dec. 2004, pp. 613-616.