Optimization of extrinsic source/drain resistance in ultrathin body double-gate FETs

IEEE Transactions on Nanotechnology

Volumn 2, Issue 4, 2003, Pages 265-270

  Shenoy, Rohit S ^a   Saraswat, Krishna C ^a  

^a Stanford University   (United States)

Author keywords

Double gate MOSFETs; MOS device scaling; MOS devices; MOSFETs; Series resistance; Silicon; Simulation

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC RESISTANCE; ELECTRON TUNNELING; ELECTROSTATICS; MOS DEVICES; OPTIMIZATION; SILICON;

MOS DEVICE SCALING; SERIES RESISTANCE;

GATES (TRANSISTOR);

EID: 3042723369     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2003.820780     Document Type: Conference Paper

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