Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors

IEEE Electron Device Letters

Volumn 28, Issue 3, 2007, Pages 211-213

  Fang, W W ^a   Singh, N ^a   Nguyen, H S ^a   Rustagi, S C ^a   Lc, G Q ^a   Balasubramanian, N ^a   Kwong, D L ^a   Bera, L K ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

Gate all around (GAA); MOSFETs; nanowire (NW); SiGe; vertically stacked NW array

Indexed keywords

EID: 85008006353     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/LED.2007.891268     Document Type: Article

References (17)

1. S. D. Suk, S.-Y. Lee, S.-M. Kim, E.-J. Yoon, M.-S. Kim, M. Li, C. W. Oh, K. H. Yeo, S. H. Kim, D.-S. Shin, K.-H. Lee, H. S. Park, J. N. Han, C. J. Park, J.-B. Park, D.-W. Kim, D. Park, and B.-I. Ryu, “High performance 5 nm radius twin silicon nanowire MOSFET (TSNWFET): Fabrication on bulk si wafer, characteristics, and reliability,” in IEDM Tech. Dig., 2005, pp. 717–720.
2. E. Gnani, S. Reggiani, M. Rudan, and G. Baccarani, “Design considerations and comparative investigations of ultra-thin SOI, double-gate and cylindrical nanowire FETS,” in Proc. ESSDERC, 2006, pp. 371–374.
3. Y. Cui, Z. Zhong, D. Wang, W. U. Wang, and C. M. Lieber, “High performance silicon nanowire field effect transistors,” Nano Lett., vol. 3, no. 2, pp. 149–152, 2003.
4. N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, “High-performance fully depleted silicon nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices,” IEEE Electron Device Lett., vol. 27, no. 5, pp. 383–386, May 2006.
5. Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King, J. Bokor, and C. Hu, “Sub-20 nm CMOS FinFET technologies,” in IEDM Tech. Dig., 2001, pp. 421–424.
6. Y. Wu and P. Yang, “Germanium nanowire growth via simple vapor transport,” Chem. Mater, vol. 12, no. 3, pp. 605–607, 2000.
7. X. Duan and C. M. Lieber, “General synthesis of compound semiconductor nanowires,” Adv. Mater., vol. 12, no. 4, pp. 298–302, Feb. 2000.
8. Y. Huang and C. M. Lieber, “Integrated nanoscale electronics and optoelectronics: Exploring nanoscale science and technology through semiconductor nanowires,” Pure Appl. Chem., vol. 76, no. 12, pp. 2051–2068, Dec. 2004.
9. M. Law, J. Goldberger, and P. Yang, “Semiconductor nanowires and nanotubes,” Annu. Rev. Mater. Res., vol. 34, pp. 83–122, Aug. 2004.
10. G. Li, N. Xi, H. Chen, A. Saeed, and M. Yu, “Assembly of nanostructure using AFM based nanomanipulation system,” in Proc. IEEE Int. Conf. Robot. Autom., 2004, vol. 1, pp. 428–433.
11. S.-Y. Lee, E.-J. Yoon, D.-S. Shin, S.-M. Kim, S.-D. Suk, M.-S. Kim, D. -W. Kim, D. Park, K. Kim, and B.-I. Ryu, “Sub-25 nm single-metal gate CMOS multi-bridge-channel MOSFET (MBCFET) for high performance and low power application,” in VLSI Symp. Tech. Dig., 2005, pp. 154–155.
12. S.-Y. Lee, E.-J. Yoon, S.-M. Kim, C. W. Oh, M. Li, J.-D. Choi, K. -H. Yeo, M.-S. Kim, H.-J. Cho, S.-H. Kim, D.-W. Kim, D. Park, and K. Kim, “A novel sub-50 nm multi-bridge-channel MOSFET (< BCFET) with extremely high performance,” in VLSI Symp. Tech. Dig., 2004, pp. 200–201.
13. E.-J. Yoon, S.-Y. Lee, S.-M. Kim, M.-S. Kim, S. H. Kim, L. Ming, S. Suk, K. Yeo, C. W. Oh, J.-D. Choe, D. Choi, D.-W. Kim, D. Park, K. Kim, and B.-I. Ryu, “Sub 30 nm multi-bridge-channel MOSFET (MBCFET) with metal gate electrode for ultra high performance application,” in IEDM Tech. Dig., 2004, pp. 627–630.
14. P.-E. Hellberg, S.-L. Zhang, F. M. D’Herule, and C. S. Petersson, “Oxidation of silicon-germanium alloys: I. An experimental study,” Appl. Phys. Lett., vol. 82, no. 11, pp. 5773–5778, 1997.
15. T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, and S. Takagi, “[110]-surface strained-SOI CMOS devices,” IEEE Trans. Electron Devices, vol. 52, no. 3, pp. 367–374, Mar. 2005.
16. R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz, and M. Radosavljevic, “Benchmarking nanotechnology for high-performance and low-power logic transistor applications,” IEEE Trans. Nanotechnol., vol. 4, no. 2, pp. 153–158, Mar. 2005.
17. [Online]. Available: http://download.intel.com/education/highered/curriculum/packaging/Lect04.ppt, pp. 39–42.