Explanation of the charge-trapping properties of silicon nitride storage layers for NVM devices part I: Experimental evidences from physical and electrical characterizations

IEEE Transactions on Electron Devices

Volumn 58, Issue 8, 2011, Pages 2483-2489

  Vianello, Elisa ^a,b   Driussi, Francesco ^a   Perniola, L ^b   Molas, Gabriel ^b   Colonna, Jean Philippe ^b   De Salvo, B ^b   Selmi, Luca ^a  

^a UNIVERSITY OF UDINE   (Italy)

^b Atomic and Alternative Energies Commission   (France)

Author keywords

Charge trapping; nonvolatile memory devices; silicon nitride (SiN)

Indexed keywords

ELECTRICAL CHARACTERISTIC; ELECTRICAL CHARACTERIZATION; EXPERIMENTAL EVIDENCE; GATE STACKS; HYDROGEN CONTENTS; MATERIAL ANALYSIS; NITRIDE STORAGE; NON-VOLATILE MEMORY APPLICATION; NONVOLATILE MEMORY DEVICES; PHYSICAL AND ELECTRICAL CHARACTERIZATIONS; PHYSICS-BASED; PROGRAM/ERASE; STORAGE LAYERS;

CHARACTERIZATION; IODINE; NONVOLATILE STORAGE; SILICON NITRIDE; STOICHIOMETRY;

ELECTRIC PROPERTIES;

EID: 79960841559     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2140116     Document Type: Article

References (40)

1. K. Kim, "Technology challenges for deep-nano semiconductor," in Proc. IMW, 2010, pp. 1-2.
2. 3 with TaN metal gate for multi-giga bit flash memories," in IEDM Tech. Dig., 2003, p. 613.
3. R. van Schaijk, M. Slotboom, M. van Duuren, D. Dormans, N. Akil, R. Beurze, F. Neuilly, W. Baks, A. Miranda, and P. Tello, "Low voltage and low power embedded 2T-SONOS flash memories improved by using P-type devices and high-k materials," Solid State Electron., vol. 49, no. 11, pp. 1849-1856, Nov. 2005. (Pubitemid 41690871)
4. A. Strum, T. Mahlen, and Y. Roizin, "Non-volatile memories in the foundry business," in Proc. IMW, 2010, pp. 3-6.
5. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, "NROM: A novel localized trapping, 2-bit nonvolatile memory cell," IEEE Electron Device Lett., vol. 21, no. 11, pp. 543-545, Nov. 2000. (Pubitemid 32031234)
6. B. Eitan, A. Shappir, and I. Bloom, "Will charge trapping become the NVM technology of choice?" Oral Present. NVSMW/ICMTD, 2008.
7. T.-H. Hsu, H.-T. Lue, E.-K. Lai, J.-Y. Hsieh, S.-Y. Wang, L.-W. Yang, Y.-C. King, T. Yang, K.-C. Chen, K.-Y. Hsieh, R. Liu, and C.-Y. Lu, "A high-speed BE-SONOS NAND flash utilizing the field-enhancement effect of FinFET," in IEDM Tech. Dig., 2007, pp. 913-916.
8. N. Goel, D. Gilmer, H. Park, V. Diaz, Y. Sun, J. Price, C. Park, P. Pianetta, P. Kirsch, and R. Jammy, "Erase and retention improvements in charge trap flash through engineered charge storage layer," IEEE Electron Device Lett., vol. 30, no. 3, pp. 216-218, Mar. 2009.
9. Y. Wang and M. White, "An analytical retention model for SONOS nonvolatile memory devices in the excess electron state," Solid State Electronics, vol. 49, no. 1, pp. 97-107, Jan. 2005.
10. E. Vianello, F. Driussi, P. Palestri, A. Arreghini, D. Esseni, L. Selmi, N. Akil, M. van Duuren, and D. Golubovi, "Impact of the charge transport in the conduction band on the retention of Si-Nitride based memories," in Proc. IEEE ESSDERC, 2008, pp. 107-110.
11. A. Furnémont, A. Cacciato, L. Breuil, M. Rosmeulen, H. Maes, K. D. Mayer, and J. van Houdt, "Physical Understanding and modeling of SANOS retention in programmed state," Solid State Electron., vol. 52, no. 4, pp. 577-583, Apr. 2008.
12. E. Nowak, E. Vianello, L. Perniola, M. Bocquet, G. Molas, R. Kies, M. Gely, G. Ghibaudo, B. D. Salvo, G. Reimbold, and F. Boulanger, "Charge localization during program and retention in nitrided read only memory-like nonvolatile memory devices," Jpn. J. Appl. Phys., vol. 49, pp. 04DD12-16, 2010.
13. M. Janai, B. Eitan, A. Shappir, E. Lusky, I. Bloom, and G. Cohen, "Data retention reliability model of NROMnonvolatile memory products," IEEE Trans. Device Mater. Rel., vol. 4, no. 3, pp. 404-415, Sep. 2004.
14. A. Furnémont,M. Rosmeulen, K. V. der Zanden, J. V. Houdt, K. D.Meyer, and H. Maes, "Root cause of charge loss in a nitride-based localized trapping memory cell," IEEE Trans. Electron Devices, vol. 54, no. 6, pp. 1351-1359, Jun. 2007. (Pubitemid 46864770)
15. S. Sandhya, U. Ganguly, N. Chattar, C. Olsen, S. M. Seutter, L. D. R. Hung, J. M. Vasi, and S. Mahapatra, "Effect of SiN on performance and reliability of charge trap flash (CTF) under Fowler-Nordheim tunneling program/erase operation," IEEE Electron Device Lett., vol. 30, no. 2, pp. 171-173, Feb. 2009.
16. G. V. den Bosch, A. Furnémont, M. B. Zahid, R. Degreave, L. Breuil, A. Cacciato, A. Rothschild, C. Olsen, U. Ganguly, and J. V. Houdt, "Nitride engineering for improved erase performance and retention of TANOS NAND flash memory," in Proc. IEEE NVSMW/ICMTD, 2008, pp. 128-129.
17. D. Gilmer, N. Goel, H. Park, C. Park, S. Verma, G. Bersuker, P. Lysaght, H. Tseng, P. Kirsch, K. Saraswat, and R. Jammy, "Engineering the complete MANOS-type NVM stack for best in class retention performance," in IEDM Tech. Dig., 2009, pp. 439-442.
18. E. Vianello, L. Perniola, P. Blaise, G. Molas, J. Colonna, F. Driussi, P. Palestri, D. Esseni, L. Selmi, N. Rochat, C. Licitra, D. Lafond, R. Kies, G. Reimbold, B. D. Salvo, and F. Boulanger, "New insight on the charge trapping mechanisms of SiN-based memory by atomistic simulations and electrical modeling," in IEDM Tech. Dig., 2009, pp. 83-86.
19. E. Vianello, E. Nowak, L. Perniola, F. Driussi, P. Blaise, G. Molas, B. D. Salvo, and L. Selmi, "A consistent explanation of the role of the SiN composition on the program/retention characteristics of MANOS and NROM like memories," in Proc. IMW, 2010, pp. 106-109.
20. E. Vianello, E. Nowak, D. Mariolle, N. Chevalier, L. Perniola, G. Molas, J. Colonna, F. Driussi, and L. Selmi, "Direct probing of trapped charge dynamics in SiN by kelvin force microscopy," in Proc. ICMTS, 2010, pp. 94-97.
21. M. Baklanov, M. Green, and K. Maex, Dielectric Films for Advanced Microelectronics. Chichester, U.K.: Wiley, 2007.
22. 2 interface using EELS and ellipsometric measurements," J. Electrochem. Soc., vol. 146, no. 2, pp. 780-785, 1999.
23. A. Iqbal, W. B. Jackson, C. C. Tsai, J. W. Allen, and C. W. Bates, "Electronic structure of silicon nitride and amorphous silicon/silicon nitride band offset by electron spectroscopy," J. Appl. Phys., vol. 61, no. 8, pp. 2947-2954, Apr. 1987.
24. S. Miyazaki, M. Narasaki, A. Suyama, M. Yamaoka, and H. Murakami, "Electronic structure and energy band offset for ultrathin silicon nitride on Si (100)," Appl. Surf. Sci., vol. 216, no. 1-4, pp. 252-257, 2003.
25. I. Levin, M. Kovler, Y. Roizin, M. Vofsi, R. D. Leapman, G. Goodman, N. Kawada, and M. Funahashi, "Structure, chemistry, and electrical performance of silicon oxide-nitride-oxide stacks on silicon," J. Electrochem. Soc., vol. 151, no. 12, pp. G833-G838, Oct. 2004. (Pubitemid 40006169)
26. V. Kapoor, R. Bailey, and S. Smith, "Impurities-related memory traps in silicon nitride thin films," J. Vac. Sci. Technol. A, Vac. Surf. Films, vol. 18, no. 2, pp. 305-308, Mar. 1981.
27. M. Olivier, F.Martin, A. Chabli, G. Lefeuvre, F. Conne, and N. Rohat, "Infrared study of hydrogen in ultra-thin Silicon Nitride films using multiple internal reflection spetroscopy (MIR) in 200 nm Silicon wafers," Phys. Stat. Sol. (A), vol. 175, pp. 137-143, 1999.
28. H. Dekkers and G. Beaucarne, "Molecular hydrogen formation in hydrogenated silicon nitride," Appl. Phys. Lett., vol. 89, no. 21, p. 211914, Nov. 2006.
29. M. Ohring, Material Science of Thin Films, Deposition and Structure. Mechanical Properties of Thin Films, 2nd ed. New York: Academic, 2006, ch. 12.
30. J. Laconte, F. Iker, S. Jorez, N. André, J. Proost, T. Pardoen, D. Flandre, and J.-P. Raskin, "Thin film stress extraction using micromachined structures and wafer curvature measurements," Micro Electron. Eng., vol. 76, no. 1-4, pp. 219-226, Oct. 2004.
31. X. Garros, C. Leroux, and J. Autran, "An efficient model for accurate capacitance-voltage characterization of high-k gate dielectrics using a mercury probe," Electrochem. Solid State Lett., vol. 5, no. 3, pp. F4-F6, Jan. 2002. (Pubitemid 34300679)
32. H.Wong, M. Poon, Y. Gao, and T. Kok, "Preparation of thin dielectric film for nonvolatile memory by thermal oxidation of Si-rich LPCVD nitride," J. Electrochem. Soc., vol. 148, no. 5, pp. G275-G278, May 2001. (Pubitemid 33693561)
33. A. Dalla Serra, A. Abramo, P. Palestri, L. Selmi, and F. Widdershoven, "Closed-and open-boundary models for gate-current calculation in n-MOSFETs," IEEE Trans. Electron Devices, vol. 48, no. 8, pp. 1811-1815, Aug. 2001. (Pubitemid 32732766)
34. K. Choi, P. Lysaght, H. Alshareef, C. Huffman, H.-C. Wen, R. Harris, H. Luan, P.-Y. Hung, C. Sparks, M. Cruz, K. Matthews, P. Majhi, and B. Lee, "Growth mechanism of TiN film on dielectric films and the effects on the work function," Thin Solid Films, vol. 486, no. 1/2, pp. 141-144, Aug. 2005. (Pubitemid 40952556)
35. E. Vianello, F. Driussi, A. Arreghini, P. Palestri, D. Esseni, L. Selmi, N. Akil, M. van Duuren, and D. Golubovic, "Experimental and simulation analysis of program/retention transients in Silicon Nitride-based NVM cells," IEEE Trans. Electron Devices, vol. 56, no. 9, pp. 1980-1990, Sep. 2009.
36. C. Sandhya, A. Oak, N. Chattar, A. Joshi, U. Ganguly, C. Olsen, S. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, "Impact of SiN composition variation on SANOS memory performance and reliability under NAND (FN/FN) operation," IEEE Trans. Electron Devices, vol. 56, no. 12, pp. 3123-3132, Dec. 2009.
37. M. Petersen and Y. Roizin, "Density functional theory study of deep traps in silicon nitride memories," Appl. Phys. Lett., vol. 89, no. 5, p. 053511, Jul. 2006.
38. T. H. Kim, I. H. Park, J. D. Lee, H. C. Shin, and B.-G. Park, "Electron trap density distribution of Si-rich silicon nitride extracted using the modified negative charge decay model of silicon-oxide-nitride-oxide- silicon structure at elevated temperatures," Appl. Phys. Lett., vol. 89, no. 6, p. 063508, Aug. 2006.
39. E. Vianello, F. Driussi, P. Blaise, P. Palestri, D. Esseni, L. Perniola, G. Molas, and L. Selmi, "Explanation of the charge trapping properties of silicon nitride storage layers for NVM's-Part II: Atomistic and electrical modeling," IEEE Trans. Electron Devices, submitted for publication.
40. A. Suhane, A. Arreghini, R. Degraeve, G. van den Bosch, L. Breuil, M. Zahid, M. Jurczak, K. D. Meyer, and J. Van Houdt, "Validation of retention modeling as a trap-profiling technique for SiN-based chargetrapping memories," IEEE Electron Device Lett., vol. 31, no. 1, pp. 77-79, Jan. 2010.