Root cause of charge loss in a nitride-based localized trapping memory cell

IEEE Transactions on Electron Devices

Volumn 54, Issue 6, 2007, Pages 1351-1359

  Furnémont, Arnaud ^a,b   Rosmeulen, Maarten ^a   van der Zanden, Koen ^a,c   Van Houdt, Jan ^a   De Meyer, Kristin ^a   Maes, Herman ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

Charge trapping; Nitride; Nonvolatile memory (NVM); Redistribution; Retention

Indexed keywords

CHARGE TRAPPING; ELECTRON TRAPS; ELECTRON TUNNELING; HOLE TRAPS; NITRIDES; THRESHOLD VOLTAGE;

DATA RETENTION LOSS; MEDICI SIMULATIONS;

NONVOLATILE STORAGE;

EID: 34249871917     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.895238     Document Type: Article

References (14)

1. K. Kim and J. Choi, "Future outlook of NAND flash technology for 40 nm node and beyond," in Proc. Non Volatile Semicond. Memory Workshop 2006, pp. 9-10.
2. A. Niebel, "Business outlook for the non-volatile memory market," in Proc. Non Volatile Semicond. Memory Workshop, 2006, pp. 6-7.
3. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, "NROM: A novel localized trapping, 2-bit nonvolatile memory cell," IEEE Electron Device Lett., vol. 21, no. 11, pp. 543-545, Nov. 2000.
4. W. J. Tsai, N. K. Zous, C. J. Liu, C. H. Chen, T. Wang, S. Pan, C.-Y. Lu, and S. H. Gu, "Data retention of a SONOS type two-bit storage flash memory cell," in IEDM Tech. Dig., 2001, pp. 32.6.1-32.6.4.
5. G. Tempel, R. Hagenbeck, and M. Strassburg, "Quantitative model for data retention loss at NROM nitride charge trapping devices after program/erase cycling," in Proc. Non Volatile Semicond. Memory Workshop, 2006, pp. 78-80.
6. M. Janai, B. Eitan, A. Shappir, E. Lusky, and I. Bloom, "Data retention reliability model of NROM nonvolatile memory products," IEEE Trans. Device Mater. Rel., vol. 4, no. 3, pp. 404-415, Sep. 2004.
7. A. Furnémont, M. Rosmeulen, J. Van Houdt, H. Maes, and K. De Meyer, "Cycling behavior of nitride charge profile in NROM-type memory cells," in Proc. Non Volatile Semicond. Memory Workshop, 2006, pp. 66-67.
8. D. Fuks, A. Kiv, Y. Roizin, M. Gutman, R. Avichail-Bibi, and T. Maximova, "The nature of HT Vt shift in NROM memory transistors," IEEE Trans. Electron Devices, vol. 53, no. 2, pp. 304-313, Feb. 2006.
9. Y.-H. Shih, S. C. Lee, H. T. Lue, M. D. Wu, T. H. Hsu, E. K. Lai, J. Y. Hsieh, C. W. Wu, L. W. Yang, K. Y. Hsieh, K. C. Chen, R. Liu, and C.-Y. Lu, "Highly reliable 2-bit/cell nitride trapping flash memory using a novel array-nitride-sealing ONO process," in IEDM Tech. Dig., 2005, pp. 551-554.
10. L. Lundkvist, I. Lundstrom, and C. Svensson, "Discharge of MNOS structures," Solid State Electron., vol. 16, no. 7, pp. 811-823, Jul. 1973.
11. M. Rosmeulen, L. Breuil, M. Lorenzini, L. Haspeslagh, J. Van Houdt, and K. De Meyer, "Characterization of the spatial charge distribution in local charge-trapping memory devices using the charge-pumping technique," Solid State Electron., vol. 48, no. 9, pp. 1525-1530, Sep. 2004.
12. A. Shappir, D. Levy, Y. Shacham-Diamand, E. Lusky, I. Bloom, and B. Eitan, "Spatial characterization of localized charge trapping and charge redistribution in the NROM device," Solid State Electron., vol. 48, no. 9, pp. 1489-1495, Sep. 2004.
13. M. Janai and B. Eitan, "The kinetics of degradation of data retention of post-cycled NROM non-volatile memory products," in Proc. IEEE Int. Reliab. Phys. Symp., 2005, vol. 43, pp. 175-180.
14. Y.-H. Shih, H.-T. Lue, K.-Y. Hsieh, R. Liu, and C.-Y. Lu, "A novel 2-bit/cell nitride storage flash memory with greater than 1 M P/E-cycle endurance," in IEDM Tech. Dig., 2004, pp. 881-884.