Surface passivation of III-V semiconductors for future CMOS devices-Past research, present status and key issues for future

Applied Surface Science

Volumn 256, Issue 19, 2010, Pages 5698-5707

  Hasegawa, H ^a   Akazawa, M ^a   Domanowska, A ^b   Adamowicz, B ^b  

^a HOKKAIDO UNIVERSITY   (Japan)

^b SILESIAN UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

GaAs; High k dielectric; III V semiconductor; MISFET; Photoluminescence; Surface passivation

Indexed keywords

CMOS INTEGRATED CIRCUITS; GALLIUM ARSENIDE; HIGH-K DIELECTRIC; III-V SEMICONDUCTORS; METAL INSULATOR BOUNDARIES; MIS DEVICES; MISFET DEVICES; NONDESTRUCTIVE EXAMINATION; PHOTOLUMINESCENCE; SEMICONDUCTING GALLIUM ARSENIDE; SEMICONDUCTING SILICON; TRANSISTORS;

FERMI LEVEL PINNING; GAAS; HIGH-QUALITY INTERFACE; INSULATOR-SEMICONDUCTOR INTERFACE; INTERFACE FORMATION; MISFET; NONDESTRUCTIVE METHODS; SURFACE PASSIVATION;

PASSIVATION;

EID: 77953133944     PISSN: 01694332     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.apsusc.2010.03.091     Document Type: Article

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