SRAM read/write margin enhancements using FinFETs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 6, 2010, Pages 887-900

  Carlson, Andrew ^a   Guo, Zheng ^b   Balasubramanian, Sriram ^c   Zlatanovici, Radu ^d   Liu, Tsu Jae King ^b   Nikolić, Borivoje ^b  

^a ADVANCED MICRO DEVICES   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c IBM MICROELECTRONICS   (United States)

^d CADENCE DESIGN SYSTEMS   (United States)

Author keywords

FinFET; Pass gate feedback; Pull up write gating; SRAM; Variation

Indexed keywords

32-NM NODE; AREA PENALTY; CELL DESIGN; FINFET; FINFETS; NEW DEVICES; PROCESS-INDUCED VARIATION; READ STABILITY; SHORT-CHANNEL EFFECT; SI TECHNOLOGY; SRAM CELL; SUB-THRESHOLD LEAKAGE; YIELD ENHANCEMENT;

EID: 77952958005     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2019279     Document Type: Article

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