Leakage and process variation effects in current testing on future CMOS circuits

IEEE Design and Test of Computers

Volumn 19, Issue 5, 2002, Pages 36-43

  Keshavarzi, Ali ^a,f   Tschanz, James W ^a   Narendra, Siva ^a   De, Vivek ^a   Roy, Kaushik ^b   Hawkins, Charles F ^c   Daasch, W Robert ^d   Sachdev, Manoj ^e  

^a INTEL CORPORATION   (United States)

^b PURDUE UNIVERSITY   (United States)

^c UNIVERSITY OF NEW MEXICO   (United States)

^d PORTLAND STATE UNIVERSITY   (United States)

^e UNIVERSITY OF WATERLOO   (Canada)

^f Mail Stop EY2 07 ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT LEAKAGE; DIRECT DRAIN QUIESCENT CURRENT; REVERSE BODY BIAS;

INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; LEAKAGE CURRENTS; RELIABILITY THEORY; SENSITIVITY ANALYSIS;

CMOS INTEGRATED CIRCUITS;

EID: 0036732499     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2002.1033790     Document Type: Article

References (6)

1. Intrinsic leakage in low-power deep submicron CMOS ICs
2. DDQ
3. A high-performance 180-nm generation logic technology
4. DDQ data
5. Forward body bias for microprocessors in 130-nm technology generation and beyond
6. Adaptive body bias for reducting impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage