A Fully Synchronized, Pipelined, and Re-Configurable 50Mb SRAM on 90nm CMOS Technology for Logic Applications

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2003, Pages 253-254

  Zhang, K ^a   Bhattacharya, U ^a   Ma, L ^a   Ng, Y ^a   Zheng, B ^a   Bohr, M ^a   Thompson, S ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; MICROPROCESSOR CHIPS; STATIC RANDOM ACCESS STORAGE;

GATE LENGTH TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 0141649389     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. S. Thompson et al., "A 90nm Logic Technology Featuring 50nm Strained Silicon Channel Transistors, 7 layers of Cu Interconnects, Low k ILD," IEDM Tech. Digest, Dec, 2002.
2. E. Seevinck et al., "Static-Noise Margin Analysis of MOS SRAM Cells," IEEE J. Solid-State Circuits, Vol. SC-22, pp. 748-754, Oct, 1987.
3. K. Zhang et al, "The Scaling of Data Sensing Schemes for High Speed Cache Design in Sub-0.18um Technologies," VLSI Circuits Sym. Tech. Digest, pp. 226-227, Jun, 2000.