FinFET SRAM for high-performance low-power applications

ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference

Volumn , Issue , 2004, Pages 69-72

  Joshi, Rajiv V ^a   Williams, Richard Q ^b   Nowak, Ed ^b   Kim, Keunwoo ^a   Beintner, Jochen ^b   Ludwig, T ^c   Aller, I ^c   Chuang, C ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

^c IBM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DOPING (ADDITIVES); ELECTRIC POTENTIAL; MOSFET DEVICES; PRODUCT DESIGN; SILICON; STANDBY POWER SYSTEMS; TECHNOLOGY TRANSFER;

DRAINED-INDUCED BARRIER LOWERING (DIBL); FINFET; IBM CIRCUIT SIMULATORS; LOW-POWER APPLICATIONS; SCALED OXIDES;

STATIC RANDOM ACCESS STORAGE;

EID: 17644408752     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. Kedzierski, J., et al., "High-performance symmetric-gate and CMOS-compatible Vt asymmetric gate FinFET devices," Tech. Digest., International Electron Device Meeting, 2002, pg. 411.
2. Rainey, B. A., et al., "Demonstration of FinFET CMOS Circuits," Device Research Conference 2002 Proceedings, pg. 47.
3. Nowak, E., et al., "A Functional FinFET DGCMOS SRAM Cell, Tech. Digest., International Electron Device Meeting, 2002, pg. 411.
4. 2 6T-SRAM Cell," Tech. Digest., International Electron Device Meeting, 2002, pg. 407.
5. Nowak, E., et al., "Scaling Beyond the 65nm Node with FinFET DGCMOS," Proc. Custom Integrated Circuits Conference 2003, pg.339.
6. Kimmel, R., PowerSPICE User's Guide, IBM Corp., Dept. 16A, 1580 Hopewell Jct., NY 12533-6531.
7. Compact Model Council web page, http://www.eigroup.org/cmc/soi/default. htm
8. BSIMPD MOSFET Model User's Manual, http://www-device.eecs.berkeley.edu/ bsim3soi/get2.html
9. Su, P., et al., "On the Body-Source Built-In Potential Lowering of SOI MOSFET's", IEEE Electron Device Letters, Vol. 24, No. 2, pg. 90.