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Volumn , Issue , 2007, Pages 127-132

FinFET based SRAM design for low standby power application

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON TUNNELING; ENERGY CONSERVATION; GATES (TRANSISTOR); TRANSISTORS;

EID: 34548118632     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2007.76     Document Type: Conference Paper
Times cited : (35)

References (15)
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  • 2
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  • 3
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    • FinFET-a quasi-planar double-gate MOSFET
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    • S.H. Tang et al, "FinFET-a quasi-planar double-gate MOSFET," ISSCC Digest of Technical Papers, pp. 118-119, February 2001.
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    • Tang, S.H.1
  • 4
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    • Advanced FinFET Technology: TiN Metal-gate CMOS and 3T/4T Device Integration
    • October
    • Y. X. Liu et al, "Advanced FinFET Technology: TiN Metal-gate CMOS and 3T/4T Device Integration", International SOI Conference, pp. 217-220, October 2005.
    • (2005) International SOI Conference , pp. 217-220
    • Liu, Y.X.1
  • 8
    • 33748987198 scopus 로고    scopus 로고
    • Ultra-thin (EOT=3A) and law leakage dielectrics of La-alminate directly on Si substrate fabricated by high temperature deposition
    • M. Suzuki, "Ultra-thin (EOT=3A) and law leakage dielectrics of La-alminate directly on Si substrate fabricated by high temperature deposition", International Electron Devices Meeting, pp., Dec. 2005.
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    • Suzuki, M.1
  • 9
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    • Device Scaling Limits of Si MOSFETs and Their Application Dependencies
    • March
    • D. J. Frank et al. "Device Scaling Limits of Si MOSFETs and Their Application Dependencies", IEEE Proceedings, Vol. 89, No. 3, pp. 259-288, March 2001.
    • (2001) IEEE Proceedings , vol.89 , Issue.3 , pp. 259-288
    • Frank, D.J.1
  • 11
    • 4544347719 scopus 로고    scopus 로고
    • Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology
    • M. Yamaoka, "Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology", Symposium on VLSI Circuits, pp. 288-291, 2004.
    • (2004) Symposium on VLSI Circuits , pp. 288-291
    • Yamaoka, M.1
  • 12
    • 0023437909 scopus 로고
    • Static-Noise Margin Analysis of MOS SRAM Cells
    • pps, Oct
    • E. Seevinck et al, "Static-Noise Margin Analysis of MOS SRAM Cells," JSSC, Vol. SC-22, No. 5, pps 748-754, Oct. 1987.
    • (1987) JSSC , vol.SC-22 , Issue.5 , pp. 748-754
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  • 13
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  • 14
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    • Implementing Caches in a 3D Technology for High Performance Processors
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.