Ultrathin-body SOI MOSFET for deep-sub-tenth micron era

IEEE Electron Device Letters

Volumn 21, Issue 5, 2000, Pages 254-255

  Choi, Yang Kyu ^a   Asano, Kazuya ^b   Lindert, Nick ^a   Subramanian, Vivek ^a   King, Tsu Jae ^a   Bokor, Jeffrey ^a   Chenming, Hu ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b JFE STEEL CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC RESISTANCE; ELECTRONICS PACKAGING; GATES (TRANSISTOR); SEMICONDUCTING SILICON COMPOUNDS; SILICON ON INSULATOR TECHNOLOGY;

DEEP SUB TENTH MICRON; GATE OXIDE; GATE WORK FUNCTION ENGINEERING; PARASITIC SERIES RESISTANCE;

MOSFET DEVICES;

EID: 0033750493     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.841313     Document Type: Article

References (4)

1. C. Hu, "Silicon-on-insulator for high speed ultra large scale integration," Jpn. J. Appl. Phys., vol. 33, pp. 365-369, Jan. 1994.
2. L. T. Su, J. B. Jacobs, J. E. Chung, and D. A. Antoniadis, "Short-channel effects in deep-submicrometer SO1 MOSFET's," in Proc. IEEE Int. SOI Conf., 1993, pp. 112-113.
3. B. Yu et al., "Ultra-thin-body Silicon-on-insulator MOSFET's for terabit-scale integration," in Proc. Int. Semiconductor Device Research Symp., 1997, pp. 623-626.
4. T.-J. King, J. P. McVittie, and K. C. Saraswat, "Electrical properties of heavily doped polycrystalline silicon-germanium films," IEEE Trans. Electron Devices, vol. 41, pp. 228-231, Feb. 1994.