Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2009, Pages 201-212

  Loh, Gabriel H ^a  

^a Georgia Institute of Technology   (United States)

Author keywords

B.3.1 memory structures : semiconductor memories; Design; Performance

Indexed keywords

3D ARCHITECTURES; CACHE MANAGEMENT POLICIES; DESIGN PERFORMANCE; DRAM CHIPS; IMPROVING SYSTEMS; MEMORY STRUCTURE; MEMORY WALL; MULTI-CORE PROCESSOR; NEW OPPORTUNITIES; PERFORMANCE BENEFITS; SEMICONDUCTOR MEMORY;

MICROPROCESSOR CHIPS; SEMICONDUCTOR STORAGE; THREE DIMENSIONAL;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 76749102941     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1669112.1669139     Document Type: Conference Paper

References (43)

1. T. Austin, E. Larson, and D. Ernst. SimpleScalar: An Infrastructure for Computer System Modeling. IEEE Micro Magazine, pages 59-67, February 2002.
2. M. Behar, A. Mendelson, and A. Kolodny. Trace Cache Sampling Filter. In Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques, pages 255-266, St. Louis, MO, USA, September 2005.
3. B. Black, M. M. Annavaram, E. Brekelbaum, J. DeVale, L. Jiang, G. H. Loh, D. McCauley, P. Morrow, D. W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. P. Shen, and C. Webb. Die-Stacking (3D) Microarchitecture. In Proceedings of the 39th International Symposium on Microarchitecture, Orlando, FL, December 2006.
4. D. Burger, J. R. Goodman, and A. Kägi. The Declining Effectiveness of Dynamic Caching for General-Purpose Microprocessors. Technical Report 1261, University of Wisconsin, January 1995.
5. D. Chandra, F. Guo, S. Kim, and Y. Solihin. Predicting Inter-Thread Cache Contenton on a Chip Multi-Processor Architecture. In Proceedings of the 11th International Symposium on High Performance Computer Architecture, pages 340-351, San Francisco, CA, USA, February 2005.
6. J. Chang and G. Sohi. Cooperative Cache Partitioning for Chip Multiprocessors. In Proceedings of the 21st International Conference on Supercomputing, pages 242-252, Seattle, WA, June 2007.
7. J. Cong, A. Jagannathan, Y. Ma, G. Reinman, J. Wei, and Y. Zhang. An Automated Design Flow for 3D Microarchitecture Evaluation. In Proceedings of the 11th Asia South Pacific Design Automation Conference, pages 384-389, Yokohama, Japan, January 2006.
8. J. Doweck. Inside Intel Core Microarchitecture and Smart Memory Access. White paper, Intel Corporation, 2006. http://download.intel.com/technology/ architecture/sma.pdf.
9. M. Ghosh and H.-H. S. Lee. Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs. In Proceedings of the 40th International Symposium on Microarchitecture, Chicago, IL, December 2007.
10. E. G. Hallnor and S. K. Reinhardt. A Fully Associative Software-Managed Cache Design. In Proceedings of the 27th International Symposium on Computer Architecture, pages 107-116, June 2000.
11. G. Hamerly, E. Perelman, J. Lau, and B. Calder. SimPoint 3.0: Faster and More Flexible Program Analysis. In Proceedings of the Workshop on Modeling, Benchmarking and Simulation, Madison, WI, USA, June 2005.
12. L. R. Hsu, S. K. Reinhardt, R. R. Iyer, and S. Makineni. Communist, Utilitarian, and Capitalist Cache Policies on CMPs: Caches as a Shared Resource. In Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques, pages 13-22, Seattle, WA, USA, September 2006.
13. Intel Corporation. First the Tick, Now the Tock: Next Generation Intel Microarchitecture (Nehalem). Intel White Paper, March 2008.
14. A. Jaleel, W. Hasenplaugh, M. Qureshi, J. Sebot, S. S. Jr., and J. Emer. Adaptive Insertion Policies for Managing Shared Caches. In Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, Brasov, Romania, September 2007.
15. T. H. Kgil, S. D'Souza, A. G. Saidi, N. Binkert, R. Dreslinski, S. Reinhardt, K. Flautner, and T. Mudge. PicoServer: Using 3D Stacking Technology to Enable a Compact Energy Efficient Chip Multiprocessor. In Proceedings of the 12th Symposium on Architectural Support for Programming Languages and Operating Systems, pages 117-128, San Jose, CA, USA, October 2006.
16. J. Kim, C. Nicopoulos, D. Park, R. Das, Y. Xie, N. Vijaykrishnan, M. S. Yousif, and C. R. Das. A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures. In Proceedings of the 34th International Symposium on Computer Architecture, San Diego, CA, USA, June 2007.
17. S. Kim, D. Chandra, and Y. Solihin. Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture. In Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques, pages 111-122, Antibes Juan-les-Pins, France, September 2004.
18. F. Li, C. Nicopoulos, T. Richardson, Y. Xie, V. Narayanan, and M. Kandemir. Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. In Proceedings of the 33rd International Symposium on Computer Architecture, pages 130-141, Boston, MA, USA, June 2006.
19. J. Lin, Q. Lu, X. Ding, Z. Zhang, and P. Sadayappan. Gaining Insights into Multicore Cache Partitioning: Bridging the Gap between Simulation and Real Systems. In Proceedings of the 14th International Symposium on High Performance Computer Architecture, pages 367-378, Salt Lake City, UT, USA, February 2008.
20. C. C. Liu, I. Ganusov, M. Burtscher, and S. Tiwari. Bridging the Processor-Memory Performance Gap with 3D IC Technology. IEEE Design and Test of Computers, 22(6):556-564, November-December 2005.
21. H. Liu, M. Ferdman, J. Huh, and D. Burger. Cache Bursts: A New Approach for Eliminating Dead Blocks and Increasing Cache Efficiency. In Proceedings of the 41st International Symposium on Microarchitecture, pages 222-233, Lake Como, Italy, November 2008.
22. G. H. Loh. 3D-Stacked Memory Architectures for Multi-Core Processors. In Proceedings of the 35th International Symposium on Computer Architecture, pages 453-464, Beijing, China, June 2008.
23. G. H. Loh, S. Subramaniam, and Y. Xie. Zesto: A Cycle-Level Simulator for Highly Detailed Microarchitecture Exploration. In Proceedings of the International Symposium on Performance Analysis of Systems and Software, Boston, MA, USA, April 2009.
24. G. H. Loh, Y. Xie, and B. Black. Processor Design in 3D Die-Stacking Technologies. IEEE Micro Magazine, 27(3), May-June 2007.
25. G. L. Loi, B. Agarwal, N. Srivastava, S.-C. Lin, and T. Sherwood. A Thermally-Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy. In Proceedings of the 43rd Design Automation Conference, pages 991-996, San Francisco, CA, USA, July 2006.
26. K. Luo, J. Gummaraju, and M. Franklin. Balancing Throughput and Fairness in SMT Processors. In Proceedings of the 2001 International Symposium on Performance Analysis of Systems and Software, pages 164-171, Tucson, AZ, USA, November 2001.
27. N. Madan and R. Balasubramonian. Leveraging 3D Technology for Improved Reliability. In Proceedings of the 40th International Symposium on Microarchitecture, pages 223-235, Chicago, IL, December 2007.
28. N. Madan, L. Zhao, N. Muralimanohar, A. Udipi, R. Balasubramonian, R. Iyer, S. Makineni, and D. Newell. Optimizing Communication and Capacity in a 3D Stacked Reconfigurable Cache Hierarchy. In Proceedings of the 15th International Symposium on High Performance Computer Architecture, pages 262-274, Raleigh, NC, USA, February 2009.
29. S. McFarling. Combining Branch Predictors. TN 36, Compaq Computer Corporation Western Research Laboratory, June 1993.
30. D. Park, S. Eachempati, R. Das, A. K. Mishra, Y. Xie, N. Vijaykrishnan, and C. R. Das. MIRA: A Multi-Layered On-Chip Interconnect Router Architecture. In Proceedings of the 35th International Symposium on Computer Architecture, pages 251-261, Beijing, China, June 2008.
31. K. Puttaswamy and G. H. Loh. Implementing Caches in a 3D Technology for High Performance Processors. In Proceedings of the International Conference on Computer Design, San Jose, CA, USA, October 2005.
32. M. K. Qureshi, , D. Lynch, O. Mutlu, and Y. N. Patt. A Case for MLP-Aware Cache Replacement. In Proceedings of the 33rd International Symposium on Computer Architecture, pages 167-178, Boston, MA, USA, June 2006.
33. M. K. Qureshi. Dynamic Spill-Accept for Scalable High-Performance Caching in CMPs. In Proceedings of the 15th International Symposium on High Performance Computer Architecture, pages 45-54, Raleigh, NC, USA, February 2009.
34. M. K. Qureshi and Y. N. Patt. Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches. In Proceedings of the 39th International Symposium on Microarchitecture, pages 423-432, Orlando, FL, December 2006.
35. N. Rafique, W.-T. Lin, and M. Thottethodi. Architectural Support for Operating System-Driven CMP Cache Management. In Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques, pages 2-12, Seattle, WA, USA, September 2006.
36. P. Reed, G. Yeung, and B. Black. Design Aspects of a Microprocessor Data Cache using 3D Die Interconnect Technology. In Proceedings of the International Conference on Integrated Circuit Design and Technology, pages 15-18, Austin, TX, USA, May 2005.
37. A. E. Snavely and D. Tullsen. Symbiotic Jobscheduling for a Simultaneous Multithreading Machine. In Proceedings of the 9th Symposium on Architectural Support for Programming Languages and Operating Systems, pages 234-244, Cambridge, MA, USA, November 2000.
38. H. S. Stone, J. Tuerk, and J. L. Wolf. Optimal Paritioning of Cache Memory. IEEE Transactions on Computers, 41(9):1054-1068, September 1992.
39. G. E. Suh, L. Rudolph, and S. Devadas. Dynamic Partitioning of Shared Cache Memory. Journal of Supercomputing, 28(1):7-26, 2004.
40. Sun Microsystems, Inc. UltraSPARC T2 Supplement to the UltraSPARC Architecture 2007. Order Number: 950-5556-02, September 2007.
41. S. Thoziyoor, N. Muralimanohar, J. H. Ahn, and N. P. Jouppi. CACTI 5.1. HPL 2008/20, HP Labs, April 2008.
42. Y.-F. Tsai, Y. Xie, N. Vijaykrishnan, and M. J. Irwin. Three-Dimensional Cache Design Using 3DCacti. In Proceedings of the International Conference on Computer Design, San Jose, CA, USA, October 2005.
43. Y. Xu, Y. Du, B. Zhao, X. Zhou, Y. Zhang, and J. Yang. A Low-Radix and Low-Diameter 3D Interconnection Network Design. In Proceedings of the 15th International Symposium on High Performance Computer Architecture, pages 30-42, Raleigh, NC, USA, February 2009.