Smart refresh: An enhanced memory controller design for reducing energy in conventional and 3D die-stacked DRAMs

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2007, Pages 134-145

  Ghosh, Mrinmoy ^a   Lee, Hsien Hsin S ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BASIC (PROGRAMMING LANGUAGE); CANNING; COST REDUCTION; DIES; ENERGY CONSERVATION; KETONES;

BENCHMARK PROGRAMS; BIOBENCH; DESIGN TECHNOLOGIES; ENERGY SAVINGS; INTERNATIONAL SYMPOSIUM; MEMORY CONTROLLERS; MICRO ARCHITECTURES; POWER REDUCTIONS; REDUCING ENERGY; SIMULATION RESULTS; TEMPERATURE INCREASE; TIME OUTS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 47349120126     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2007.13     Document Type: Conference Paper

References (34)

1. Artisan sram generator. http://www.artisan.com.
2. Easy Integration of Embedded DRAMs. http://www.am.necel.com/process/ edramsequences.html.
3. Intel 855PM Chipset Memory Controller Hub (MCH) DDR datasheet. ftp://download.intel.com/design/chipsets/datashts/25261303.pdf.
4. Intel 855PM Chipset Platform Design Guide. http://download.intel.com/ design/mobile/desguide/25261403.pdf.
5. ITRS Roadmap 2006 Interconnect Update. http://www.itrs.net/Links/ 2006Update/FinalToPost/09 Interconnect2006Update.pdf.
6. Micron 128Mb: x32 SDRAM data sheet. http://download.micron.com/pdf/ datasheets/ dram/sdram/128MbSDRAMx32.pdf.
7. Micron DDR2 SDRAM Registererd DIMM 2GB and 4GB data sheet. http://download.micron.com/pdf/datasheets/modules/ddr2/HTF36C256 512x72.pdf.
8. NEC 16 M-Word by 64-Bit DDR Synchronous Dynamic RAM Module Unbuffered Type Specification. http://www.nec.com.
9. Samgsung Develops 3D Memory Package that Greatly Improves Performance Using Less Space. http://www.samsung.com/PressCenter/PressRelease/PressRelease. asp?seq=20060413 0000246668.
10. Samsung 512Mb D-Die DDR SDRAM Specification. http://www.samsung.com.
11. Tezzaron Semiconductor, FaStack Technology. http://www.tezzaron.com/ technology/FaStack.htm.
12. Virtutech Simics. http://www.simics.net.
13. K. Albayraktaroglu, A. Jaleel, X. Wu, M. Franklin, B. Jacob, C.-W. Tseng, and D. Yeung. Biobench: A benchmark suite of bioinformatics applications. In Proceedings of the International Symposium on Performance Analysis of Systems and Software, 2005.
14. B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L. Jiang, G. H. Loh, D. McCaule, P. Morrow, D. W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen, and C. Webb. Die stacking (3d) microarchitecture. In Proceedings of the 39th International Symposium on Microarchitecture, pages 469.479, 2006.
15. B. Black, D. W. Nelson, C. Webb, and N. Samra. 3D Processing Technology and Its Impact on iA32 Microprocessors. In Proceeding of International Conference on Computer Design, 2004.
16. F. Catthoor. Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design. Kluwer Academic Publishers, 1998.
17. P. G. Emma, W. R. Reohr, and L.-K. Wang. Restore Tracking System for DRAM, U.S Patent No 6,839,505 B1, 2002.
18. B. Ganesh, A. Jaleel, D. Wang, and B. Jacob. Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling. Proceedings of the 13th International Symposium on High Performance Computer Architecture, 2007.
19. S. Kaxiras, Z. Hu, and M. Martonosi. Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power. In Proceedings of the 28th International Symposium on Computer Architecture, pages 240.251, 2001.
20. J. Kim and M. C. Papaefthymiou. Dynamic Memory Design for Low Data-Retention Power. In Proceedings of the International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 2000.
21. T. Kirihata, P. Parries, D. Hanson, H. Kim, J. Golz, G. Fredeman, R. Rajeevakumar, J. Griesemer, N. Robson, A. Cestero, et al. An 800-MHz Embedded DRAM With a Concurrent Refresh Mode. IEEE Journal of Solid-State circuits, 40(6):1377, 2005.
22. M. M. K. Martin, D. J. Sorin, B. M. Beckmann, M. R. Marty, M. Xu, A. R. Alameldeen, K. E. Moore, M. D. Hill, and D. A. Wood. Multifacet's General Execution-Driven Multiprocessor Simulator (GEMS) Toolset. SIGARCH Comput. Archit. News, 33(4), 2005.
23. Micron. DDR2 SDRAM SODIMM 1GB 2GB Data Sheet. http://download.micron.com/ pdf/datasheets/modules/ddr2/HTF16C64 128 256x64HG.pdf.
24. Micron. Various Methods of DRAM Refresh. http://download.micron.com/pdf/ technotes/DT30.pdf.
25. M.Viredaz and D. Wallach. Power Evaluation of a Handheld Computer: A Case Study. Technical report, Compaq WRL, 2001.
26. T. Ohsawa, K. Kai, and K. Murakami. Optimizing the DRAM refresh count for merged DRAM/logic LSIs. In Proceedings of the International Symposium on Low Power Electronics and Design, 1998.
27. J. T. Pawlowski. Intelligent refresh controller for dynamic memory devices, U.S Patent No 5,890,198 B1, 1999.
28. L. A. Polka, H. Kalyanam, G. Hu, and S. Krishnamoorthy. Package Technology to Address the Memory Bandwidth Challenge for Tera-Scale Computing. Intel Technology Journal, 11(03), 2007.
29. A. Rahman and R. Reif. System Level Performance Evaluation of Three-Dimensional Integrated Circuits. IEEE Tranactions on VLSI, 8(6):671.678, 2000.
30. S. Sait and H. Youssef. VLSI Physical Design Automation: Theory and Practice. McGraw-Hill, 1995.
31. S. P. Song. Method and system for selective DRAM refresh to reduce power consumption, U.S Patent No 6,094,705 B1, 2000.
32. R. Venkatesan, S.Herr, and E. Rotenberg. Retention-Aware Placement in DRAM (RAPID):Software Methods for Quasi-Non-Volatile DRAM. In Proceedings of the Twelfth Annual Symposium on High Performance Computer Architecture, pages 155.165, Nov. 2006.
33. D. Wang, B. Ganesh, N. Tuaycharoen, K. Baynes, A. Jaleel, and B. Jacob. DRAMsim: a memory system simulator. SIGARCH Comput. Archit. News, 33(4):100.107, 2005.
34. S. Woo, M. Ohara, E. Torrie, J. Singh, and A. Gupta. The SPLASH-2 Programs: Characterization and Methodological Considerations. In Proceedings of the 22nd International Symposium on Computer Architecture, pages 24.36, June 1995.