메뉴 건너뛰기




Volumn 2005, Issue , 2005, Pages 255-264

Trace cache sampling filter

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; POWER ELECTRONICS; RANDOM PROCESSES; SIGNAL FILTERING AND PREDICTION;

EID: 33746749348     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2005.38     Document Type: Conference Paper
Times cited : (10)

References (18)
  • 3
    • 0033719421 scopus 로고    scopus 로고
    • Wattch: A framework for architectural-level power analysis and optimizations
    • David Brooks and Vivek Tiwari and Margaret Martonosi, " Wattch: a framework for architectural-level power analysis and optimizations", in ISCA 2000 pages 83-94.
    • ISCA 2000 , pp. 83-94
    • Brooks, D.1    Tiwari, V.2    Martonosi, M.3
  • 5
    • 0034226001 scopus 로고    scopus 로고
    • SPEC CPU2000: Measuring CPU performance in the new millennium
    • J. Henning. SPEC CPU2000: Measuring CPU Performance in the New Millennium. IEEE Computer, pp. 28-35, 2000.
    • (2000) IEEE Computer , pp. 28-35
    • Henning, J.1
  • 6
    • 0003278283 scopus 로고    scopus 로고
    • The microarchitecture of the Pentium 4 processor
    • G. Hinton et al., "The microarchitecture of the Pentium 4 processor," in Intel TechnologyJournal, 2001
    • (2001) Intel TechnologyJournal
    • Hinton, G.1
  • 10
    • 0035363244 scopus 로고    scopus 로고
    • RePlay: A hardware framework for dynamic optimization
    • June
    • S. Patel and S. Lumetta, "rePlay: A Hardware Framework for Dynamic Optimization", in IEEE Trans, on Computers, 50(6), pp 590-608, June 2001
    • (2001) IEEE Trans, on Computers , vol.50 , Issue.6 , pp. 590-608
    • Patel, S.1    Lumetta, S.2
  • 11
    • 33746714400 scopus 로고
    • "Dynamic Flow Instruction Cache Memory Organized Around Trace Segments Independent of Virtual Address Line", U.S. Patent 5,381,533, Jan.
    • A. Peleg and U. Weiser. "Dynamic Flow Instruction Cache Memory Organized Around Trace Segments Independent of Virtual Address Line", U.S. Patent 5,381,533, Jan. 1995.
    • (1995)
    • Peleg, A.1    Weiser, U.2
  • 15
    • 35048814925 scopus 로고    scopus 로고
    • PARROT: Power awareness through selective dynamically optimized traces
    • Roni Rosner, Yoav Almog, Micha Moffie, Naftali Schwartz, Avi Mendelson: "PARROT: Power Awareness Through Selective Dynamically Optimized Traces", in PACS 2003: 196-214
    • PACS 2003 , pp. 196-214
    • Rosner, R.1    Almog, Y.2    Moffie, M.3    Schwartz, N.4    Mendelson, A.5
  • 16
    • 0033077095 scopus 로고    scopus 로고
    • A trace cache microarchitecture and evaluation
    • Feb.
    • E. Rotenberg, S. Bennett and J. Smith, "A Trace Cache Microarchitecture and Evaluation", in IEEE Trans. on Computers, 48(2), pp 111-120, Feb. 1999
    • (1999) IEEE Trans. on Computers , vol.48 , Issue.2 , pp. 111-120
    • Rotenberg, E.1    Bennett, S.2    Smith, J.3
  • 18
    • 0030149507 scopus 로고    scopus 로고
    • CACTI: An enhanced cache access and cycle time model
    • May
    • S.J.E. Wilton and N.P. Jouppi. "CACTI: An enhanced cache access and cycle time model." IEEE Journal of Solid-State Circuits, Vol. 31(5):677-688, May 1996.
    • (1996) IEEE Journal of Solid-state Circuits , vol.31 , Issue.5 , pp. 677-688
    • Wilton, S.J.E.1    Jouppi, N.P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.