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Volumn 2005, Issue , 2005, Pages 519-524

Three-dimensional cache design exploration using 3DCacti

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; ENERGY MODEL; GRANULARITY; THREE DIMENSIONAL INTEGRATED CIRCUITS (3D ICS);

EID: 33746603614     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2005.108     Document Type: Conference Paper
Times cited : (88)

References (18)
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    • Benini, L.1    Micheli, G.D.2
  • 2
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    • X Initiative
  • 5
    • 2942658001 scopus 로고    scopus 로고
    • Timing, energy, and thermal performance of three-dimensional integrated circuits
    • Das, S., "Timing, Energy, and Thermal Performance of Three-Dimensional Integrated Circuits", GLSVLSI 2004
    • GLSVLSI 2004
    • Das, S.1
  • 8
    • 33748559571 scopus 로고    scopus 로고
    • The revolutionary and truly 3-dimentional 25F2 SRAM technology with the smallest S3 cell, 0.16um2 and SSTFF for ultra high density SRAM
    • Jung, S.M., et al, "The Revolutionary and Truly 3-Dimentional 25F2 SRAM Technology with the Smallest S3 Cell, 0.16um2 and SSTFF for Ultra High Density SRAM", VLSI Technology Digest of Technical Papers, 2004
    • (2004) VLSI Technology Digest of Technical Papers
    • Jung, S.M.1
  • 9
    • 0003450887 scopus 로고    scopus 로고
    • Cacti 3.0: An integrated cache timing, power, and area model
    • 2
    • Shivakumar, P., et al, "Cacti 3.0: An Integrated Cache Timing, Power, and Area Model", Western Research Lab. Research Report, 2001/2.
    • (2001) Western Research Lab. Research Report
    • Shivakumar, P.1
  • 10
    • 0346076629 scopus 로고    scopus 로고
    • Contact resistance measurement of bonded copper interconnects for three-dimensional integration technology
    • Chen, K. N., et al, "Contact Resistance Measurement of Bonded Copper Interconnects for Three-Dimensional Integration Technology", IEEE Electron Devices Letters, 25 (1), 2004
    • (2004) IEEE Electron Devices Letters , vol.25 , Issue.1
    • Chen, K.N.1
  • 12
    • 4544226086 scopus 로고    scopus 로고
    • A SRAM design on 65nm CMOS technology with integrated leakage reduction scheme
    • Zhang, K., et al, "A SRAM Design on 65nm CMOS technology with Integrated Leakage Reduction Scheme", IEEE Symp. On VLSI Circuits Digest of Technical Papers, 2004
    • (2004) IEEE Symp. on VLSI Circuits Digest of Technical Papers
    • Zhang, K.1
  • 16
    • 0003850954 scopus 로고    scopus 로고
    • Princeton-Hall publication
    • nd Edition, Princeton-Hall publication, 2002
    • (2002) nd Edition
    • Rabaey, J.1
  • 17
    • 16244408347 scopus 로고    scopus 로고
    • Analytical models for leakage power estimation of memory array structures
    • Mamidipaka, M., "Analytical Models for Leakage Power Estimation of Memory Array Structures", CODES+ISSS, 2004
    • (2004) CODES+ISSS
    • Mamidipaka, M.1
  • 18
    • 16244382518 scopus 로고    scopus 로고
    • Fabrication and characteristics of novel load PMOS SSTFT (Stacked single-crystal thin film transistor) for 3-dimentional SRAM memory cell
    • Kang, Y. H., et al, "Fabrication and Characteristics of Novel Load PMOS SSTFT (Stacked Single-crystal Thin Film Transistor) for 3-dimentional SRAM Memory Cell ", SOI Conference, 2004
    • (2004) SOI Conference
    • Kang, Y.H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.