Implementing caches in a 3D technology for high performance processors

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn 2005, Issue , 2005, Pages 525-532

  Puttaswamy, Kiran ^a   Loh, Gabriel H ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b School of Chemistry and Biochemistry   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GLOBAL ROUTING; MICROARCHITECTURE DESIGN; THREE DIMENSIONAL INTEGRATED TECHNOLOGY; WORDLINES;

COMPUTER ARCHITECTURE; INTEGRATED CIRCUITS; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; STATIC RANDOM ACCESS STORAGE;

CACHE MEMORY;

EID: 33748563957     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2005.65     Document Type: Conference Paper

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