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Volumn 2006, Issue , 2006, Pages 167-177

A case for MLP-aware cache replacement

Author keywords

[No Author keywords available]

Indexed keywords

CACHE REPLACEMENT; LONG LATENCY MEMORY ACCESSES; MEMORY LEVEL PARALLELISM (MLP); SAMPLING BASED ADAPTIVE REPLACEMENT (SBAR);

EID: 33845874613     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2006.5     Document Type: Conference Paper
Times cited : (222)

References (25)
  • 2
    • 0003003638 scopus 로고
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    • (1966) IBM Systems Journal , pp. 78-101
    • Belady, L.A.1
  • 4
    • 22944446075 scopus 로고    scopus 로고
    • Kilo-instruction processors: Overcoming the memory wall
    • May
    • A. Cristal et al. Kilo-instruction processors: Overcoming the memory wall. IEEE Micro, 25(3), May 2005.
    • (2005) IEEE Micro , vol.25 , Issue.3
    • Cristal, A.1
  • 13
    • 0003506711 scopus 로고
    • Technical Report TN-36, Digital Western Research Laboratory, June
    • S. McFarling. Combining branch predictors. Technical Report TN-36, Digital Western Research Laboratory, June 1993.
    • (1993) Combining Branch Predictors
    • McFarling, S.1
  • 16
    • 0028457070 scopus 로고
    • The K-server dual and loose competetiveness for paging
    • N. Young. The K-server dual and loose competetiveness for paging. Agorithmica, 11(2):525-541, 1994.
    • (1994) Agorithmica , vol.11 , Issue.2 , pp. 525-541
    • Young, N.1
  • 23
    • 1342320051 scopus 로고    scopus 로고
    • The memory gap and the future of high performance memories
    • Mar.
    • M. V. Wilkes. The memory gap and the future of high performance memories.ACM Computer Architecture News, 29(1):2-7, Mar. 2001.
    • (2001) ACM Computer Architecture News , vol.29 , Issue.1 , pp. 2-7
    • Wilkes, M.V.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.