Adaptive spill-receive for robust high-performance caching in CMPs

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2009, Pages 45-54

  Qureshi, Moinuddin K ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

QUALITY OF SERVICE;

AVERAGE THROUGHPUT; CAPACITY SHARING; CHIP MULTIPROCESSORS; EFFICIENT CAPACITIES; LAST-LEVEL CACHES; PERFORMANCE BENEFITS; STORAGE OVERHEAD; WORST-CASE PERFORMANCE;

COMPUTER ARCHITECTURE;

EID: 64949187933     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2009.4798236     Document Type: Conference Paper

References (11)

1. B. M. Beckmann et al. ASR: Adaptive selective replication for CMP caches. In MICRO-2006.
2. J. Chang and G. S. Sohi. Cooperative cache partitioning for chip multiprocessors. In ICS-2007.
3. J. Chang and G. S. Sohi. Cooperative caching for chip multiprocessors. In ISCA-2006.
4. Z. Chishti et al. Optimizing replication, communication, and capacity allocation in CMPs. In ISCA-2005.
5. M. D. Dahlin et al. Cooperative caching: using remote client memory to improve file system performance. In OSDI-1994.
6. A. Jaleel et al. Adaptive insertion policies for managing shared caches. In PACT-2008.
7. P. Kongetira et al. Niagara: A 32-way multithreaded SPARC processor. IEEE Micro, 25(2):21-29, 2005.
8. R. Kumar, V. Zyuban, and D.M. Tullsen. Interconnections in multi-core architectures: Understanding mechanisms, overheads and scaling. In ISCA-2005.
9. K. Luo, J. Gummaraju, and M. Franklin. Balancing throughput and fairness in SMT processors. In ISPASS-2001.
10. M. K. Qureshi et al. Adaptive insertion policies for highperformance caching. In ISCA-2007.
11. M. K. Qureshi et al. A case for MLP-aware cache replacement. In ISCA-2006.