Zesto: A cycle-level simulator for highly detailed microarchitecture exploration

ISPASS 2009 - International Symposium on Performance Analysis of Systems and Software

Volumn , Issue , 2009, Pages 53-54

  Loh, Gabriel H ^a   Subramaniam, Samantika ^a   Xie, Yuejian ^a  

^a Georgia Institute of Technology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BYPASS NETWORKS; CACHE COHERENCE; LOOKUPS; LOW LEVEL; MICRO ARCHITECTURES; MODERN PROCESSORS; MULTI CORE; OUT OF ORDER; PIPELINE MODELS; RESOURCE MANAGEMENT; SIMPLIFIED MODELS; TIMING SIMULATORS;

COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; RESOURCE ALLOCATION; SCHEDULING;

SIMULATORS;

EID: 70349190964     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2009.4919638     Document Type: Conference Paper

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