Leveraging 3D technology for improved reliability

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2007, Pages 223-235

  Madan, Niti ^a   Balasubramonian, Rajeev ^a  

^a Department of Electrical and Computer Engineering

Author keywords

3D die stacking; Dynamic timing errors; On chip temperature; Parameter variation; Power efficient microarchitecture; Redundant multi threading; Reliability; Soft errors

Indexed keywords

3D TECHNOLOGY; CHIP TECHNOLOGIES; DYNAMIC TIMING; ERROR RESILIENCE (ER); INTERNATIONAL SYMPOSIUM; L2 CACHE ORGANIZATION; MICRO ARCHITECTURES; ON-CHIP WIRES; PARAMETER VARIATIONS; PERFORMANCE LOSSES; PROCESS TECHNOLOGIES; PROCESS TECHNOLOGIES (CO); PROCESSOR PERFORMANCE; PROCESSOR RELIABILITY; REDUCED POWER CONSUMPTION; RELIABLE PROCESSORS; SINGLE CHIPS; SUPPLY VOLTAGES; TECHNOLOGY SCALING; TEMPERATURE INCREASE; THREE DIMENSIONAL (3-D) INTEGRATION; TRANSIENT FAULTS; WITHIN DIE (WID);

COMPUTER SYSTEMS; ERROR ANALYSIS; ERRORS; MICROPROCESSOR CHIPS; QUALITY ASSURANCE; REDUNDANCY; RELIABILITY; TECHNOLOGY;

DIES;

EID: 47349097129     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2007.31     Document Type: Conference Paper

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