An automated design flow for 3D microarchitecture evaluation

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2006, Issue , 2006, Pages 384-389

  Cong, Jason ^a   Jagannathan, Ashok ^a   Ma, Yuchun ^a,b   Reinman, Glenn ^a   Wei, Jie ^a   Zhang, Yan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; ENERGY DISSIPATION; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; ROUTERS; THERMOANALYSIS;

FLOORPLANNING; INTERCONNECT DELAYS; MICROARCHITECTURAL DESIGNS; ROUTING;

INTEGRATED CIRCUIT LAYOUT;

EID: 33748631273     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118395     Document Type: Conference Paper

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